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MC74HC368N PDF预览

MC74HC368N

更新时间: 2024-11-27 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 147K
描述
Hex 3-State Inverting Buffer with Separate 2-Bit and 4-Bit Sections

MC74HC368N 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.28其他特性:ONE FUNCTION WITH TWO BITS
系列:HC/UHJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.175 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:6功能数量:1
端口数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):29 ns
认证状态:Not Qualified座面最大高度:4.44 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

MC74HC368N 数据手册

 浏览型号MC74HC368N的Datasheet PDF文件第2页浏览型号MC74HC368N的Datasheet PDF文件第3页浏览型号MC74HC368N的Datasheet PDF文件第4页浏览型号MC74HC368N的Datasheet PDF文件第5页 
SEMICONDUCTOR TECHNICAL DATA  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
High–Performance Silicon–Gate CMOS  
1
The MC74HC368 is identical in pinout to the LS368. The device inputs are  
compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
This device is arranged into 2–bit and 4–bit sections, each having its own  
active–low Output Enable. When either of the enables is high, the affected  
buffer outputs are placed into high–impedance states. The HC368 has  
inverting outputs.  
ORDERING INFORMATION  
MC74HCXXXN Plastic  
PIN ASSIGNMENT  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
OUTPUT  
1
2
16  
15  
V
CC  
OUTPUT  
ENABLE 2  
ENABLE 1  
A0  
Low Input Current: 1 µA  
Y0  
A1  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
A5  
Y5  
A4  
Y4  
A3  
Y3  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
Y1  
Chip Complexity: 80 FETs or 20 Equivalent Gates  
A2  
Y2  
LOGIC DIAGRAM  
GND  
2
4
3
5
A0  
A1  
Y0  
Y1  
FUNCTION TABLE  
Inputs  
Enable 1,  
Output  
Enable 2  
A
Y
6
7
9
A2  
A3  
A4  
Y2  
Y3  
Y4  
L
L
H
L
H
X
H
L
Z
10  
12  
X = don’t care  
Z = high–impedance  
11  
14  
13  
A5  
Y5  
1
OUTPUT ENABLE 1  
OUTPUT ENABLE 2  
PIN 16 = V  
CC  
PIN 8 = GND  
15  
10/95  
REV 6  
Motorola, Inc. 1995  

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