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MC74HC367ADR2G PDF预览

MC74HC367ADR2G

更新时间: 2024-10-29 01:05:35
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 129K
描述
Hex 3-State Noninverting Buffer

MC74HC367ADR2G 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:51 weeks
风险等级:5.69控制类型:ENABLE LOW
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A湿度敏感等级:1
位数:4功能数量:2
端口数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
电源:2/6 VProp。Delay @ Nom-Sup:36 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

MC74HC367ADR2G 数据手册

 浏览型号MC74HC367ADR2G的Datasheet PDF文件第2页浏览型号MC74HC367ADR2G的Datasheet PDF文件第3页浏览型号MC74HC367ADR2G的Datasheet PDF文件第4页浏览型号MC74HC367ADR2G的Datasheet PDF文件第5页浏览型号MC74HC367ADR2G的Datasheet PDF文件第6页浏览型号MC74HC367ADR2G的Datasheet PDF文件第7页 
MC74HC367A  
Hex 3-State Noninverting  
Buffer with Separate 2-Bit  
and 4-Bit Sections  
HighPerformance SiliconGate CMOS  
http://onsemi.com  
The MC74HC367A is identical in pinout to the LS367. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
MARKING  
DIAGRAMS  
16  
This device is arranged into 2bit and 4bit sections, each having its  
own activelow Output Enable. When either of the enables is high, the  
affected buffer outputs are placed into highimpedance states. The  
HC367A has noninverting outputs.  
SOIC16  
D SUFFIX  
CASE 751B  
HC367AG  
AWLYWW  
16  
1
1
16  
Features  
TSSOP16  
DT SUFFIX  
CASE 948F  
HC  
367A  
ALYWG  
G
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
Low Input Current: 1 mA  
High Noise Immunity Characteristic of CMOS Devices  
These are PbFree Devices  
16  
1
1
A
= Assembly Location  
= Wafer Lot  
= Year  
WL, L  
YY, Y  
WW, W = Work Week  
G or G  
= PbFree Package  
(Note: Microdot may be in either location)  
2
4
3
5
A0  
A1  
Y0  
Y1  
PIN ASSIGNMENT  
OUTPUT  
ENABLE 1  
1
2
3
4
5
6
7
8
16  
15  
V
CC  
OUTPUT  
ENABLE 2  
A0  
6
7
9
A2  
A3  
A4  
Y2  
Y3  
Y4  
Y0  
A1  
14 A5  
13 Y5  
12 A4  
11 Y4  
10 A3  
10  
12  
Y1  
11  
A2  
Y2  
14  
13  
A5  
Y5  
GND  
9
Y3  
1
FUNCTION TABLE  
OUTPUT ENABLE 1  
OUTPUT ENABLE 2  
PIN 16 = V  
CC  
PIN 8 = GND  
Inputs  
Enable 1,  
Output  
15  
Enable 2  
A
Y
Figure 1. Logic Diagram  
L
L
H
L
H
X
L
H
Z
X = don’t care  
Z = high impedance  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
June, 2013 Rev. 4  
MC74HC367A/D  

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