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MC74HC367ADTEL PDF预览

MC74HC367ADTEL

更新时间: 2024-10-28 13:11:19
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
6页 159K
描述
IC,BUFFER/DRIVER,DUAL,2-BIT/4-BIT,HC-CMOS,TSSOP,16PIN,PLASTIC

MC74HC367ADTEL 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:TSSOP, TSSOP16,.25Reach Compliance Code:unknown
风险等级:5.92控制类型:ENABLE LOW
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A位数:6
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:2/6 VProp。Delay @ Nom-Sup:36 ns
认证状态:Not Qualified子类别:Bus Driver/Transceivers
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUALBase Number Matches:1

MC74HC367ADTEL 数据手册

 浏览型号MC74HC367ADTEL的Datasheet PDF文件第2页浏览型号MC74HC367ADTEL的Datasheet PDF文件第3页浏览型号MC74HC367ADTEL的Datasheet PDF文件第4页浏览型号MC74HC367ADTEL的Datasheet PDF文件第5页浏览型号MC74HC367ADTEL的Datasheet PDF文件第6页 
SEMICONDUCTOR TECHNICAL DATA  
N SUFFIX  
PLASTIC PACKAGE  
16–LEAD  
CASE 648–08  
High–Performance Silicon–Gate CMOS  
D SUFFIX  
SOIC PACKAGE  
16–LEAD  
The MC74HC367A is identical in pinout to the LS367. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
CASE 751B–05  
DT SUFFIX  
TSSOP PACKAGE  
16–LEAD  
This device is arranged into 2–bit and 4–bit sections, each having its own  
active–low Output Enable. When either of the enables is high, the affected  
buffer outputs are placed into high–impedance states. The HC367A has  
noninverting outputs.  
CASE 948F–01  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
ORDERING INFORMATION  
MC74HCXXXAN  
MC74HCXXXAD  
MC74HCXXXADT  
Plastic  
SOIC  
TSSOP  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
Chip Complexity: 92 FETs or 23 Equivalent Gates  
PIN ASSIGNMENT  
OUTPUT  
1
2
16  
15  
V
CC  
OUTPUT  
ENABLE 2  
ENABLE 1  
A0  
LOGIC DIAGRAM  
Y0  
A1  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
A5  
Y5  
A4  
Y4  
A3  
Y3  
2
4
3
5
A0  
A1  
Y0  
Y1  
Y1  
A2  
Y2  
6
7
9
A2  
A3  
Y2  
Y3  
GND  
10  
12  
FUNCTION TABLE  
11  
A4  
A5  
Y4  
Y5  
Inputs  
Enable 1,  
Enable 2  
Output  
14  
13  
A
Y
L
L
H
L
H
X
L
H
Z
1
OUTPUT ENABLE 1  
OUTPUT ENABLE 2  
PIN 16 = V  
CC  
PIN 8 = GND  
15  
X = don’t care  
Z = high impedance  
This document contains information on a new product. Specifications and information herein are subject to  
change without notice.  
3/97  
REV 0.1  
Motorola, Inc. 1997  

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