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MC74HC367ADTR2 PDF预览

MC74HC367ADTR2

更新时间: 2024-10-28 20:09:19
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
6页 190K
描述
HC/UH SERIES, 6-BIT DRIVER, TRUE OUTPUT, PDSO16, PLASTIC, TSSOP-16

MC74HC367ADTR2 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.15系列:HC/UH
JESD-30 代码:R-PDSO-G16长度:5 mm
逻辑集成电路类型:BUS DRIVER位数:6
功能数量:1端口数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟(tpd):180 ns
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

MC74HC367ADTR2 数据手册

 浏览型号MC74HC367ADTR2的Datasheet PDF文件第2页浏览型号MC74HC367ADTR2的Datasheet PDF文件第3页浏览型号MC74HC367ADTR2的Datasheet PDF文件第4页浏览型号MC74HC367ADTR2的Datasheet PDF文件第5页浏览型号MC74HC367ADTR2的Datasheet PDF文件第6页 
MC74HC367A  
Hex 3−State Noninverting  
Buffer with Separate 2−Bit  
and 4−Bit Sections  
HighPerformance SiliconGate CMOS  
http://onsemi.com  
The MC74HC367A is identical in pinout to the LS367. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
This device is arranged into 2bit and 4bit sections, each having its  
own activelow Output Enable. When either of the enables is high, the  
affected buffer outputs are placed into highimpedance states. The  
HC367A has noninverting outputs.  
N SUFFIX  
PLASTIC PACKAGE  
16LEAD  
CASE 64808  
D SUFFIX  
SOIC PACKAGE  
16LEAD  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
CASE 751B05  
DT SUFFIX  
TSSOP PACKAGE  
16LEAD  
Low Input Current: 1 μA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
CASE 948F01  
ORDERING INFORMATION  
MC74HCXXXAN  
MC74HCXXXAD  
MC74HCXXXADT  
Plastic  
SOIC  
TSSOP  
Chip Complexity: 92 FETs or 23 Equivalent Gates  
LOGIC DIAGRAM  
2
4
3
5
PIN ASSIGNMENT  
A0  
A1  
Y0  
Y1  
OUTPUT  
ENABLE 1  
1
2
3
4
5
6
7
8
16  
15  
V
CC  
OUTPUT  
ENABLE 2  
A0  
Y0  
14 A5  
13 Y5  
12 A4  
11 Y4  
10 A3  
6
7
9
A2  
A3  
A4  
Y2  
Y3  
Y4  
A1  
10  
12  
Y1  
A2  
11  
Y2  
GND  
9
Y3  
14  
13  
A5  
Y5  
1
OUTPUT ENABLE 1  
OUTPUT ENABLE 2  
FUNCTION TABLE  
PIN 16 = V  
CC  
PIN 8 = GND  
15  
Inputs  
Enable 1,  
Output  
Enable 2  
A
Y
L
L
H
L
H
X
L
H
Z
X = don’t care  
Z = high impedance  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
June, 2006 Rev. 2  
MC74HC367A/D  

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