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MC74HC354NS PDF预览

MC74HC354NS

更新时间: 2024-11-28 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 复用器锁存器
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9页 210K
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MC74HC354NS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
20  
20  
1
High–Performance Silicon–Gate CMOS  
The MC54/74HC354 is identical in pinout to the LS354. The device  
inputs are compatible with Standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
The HC354 selects one of eight latched binary Data Inputs, as deter-  
mined by the Address Inputs. The information at the Data Inputs is stored  
in the transparent 8–bit Data Latch when the Data–Latch Enable pin is  
held high. The Address information may be stored in the transparent  
Address Latch, which is enabled by the active–high Address–Enable pin.  
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
The device outputs are placed in high–impedance states when Output  
Enable 1 is high, Output Enable 2 is high, or Output Enable 3 is low.  
ORDERING INFORMATION  
MC54HCXXXJ  
MC74HCXXXN  
MC74HCXXXDW  
Ceramic  
Plastic  
SOIC  
The HC354 has a clocked Data Latch that is not transparent.  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2 to 6V  
Pinout: 20–Lead Package (Top View)  
Low Input Current: 1µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With the JEDEC Standard No. 7A Requirements  
Chip Complexity: 326 FETs or 81.5 Equivalent Gates  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
V
Y
Y
1
2
3
4
5
20  
19  
18  
17  
16  
CC  
LOGIC DIAGRAM  
OE3  
OE2  
OE1  
8
D0  
7
6
7
15  
D1  
6
D2  
8–BIT  
DATA  
LATCH  
(TRANS–  
PARENT)  
14 A0  
5
4
3
2
1
19  
18  
8–BIT  
MULTI–  
PLEXER  
3–STATE  
OUTPUT  
CONTROL  
3–STATE  
DATA  
OUTPUTS  
DATA  
INPUTS  
D3  
D4  
D5  
D6  
D7  
Y
Y
A1  
A2  
8
9
13  
12  
Data–Latch  
Enable  
Address–Latch  
Enable  
GND  
10  
11  
9
DATA–LATCH  
ENABLE  
14  
13  
12  
ADDRESS  
LATCH  
(TRANS–  
PARENT)  
A0  
ADDRESS  
INPUTS  
A1  
A2  
11  
PIN 20 = V  
CC  
PIN 10 = GND  
ADDRESS–LATCH  
ENABLE  
15  
16  
17  
OE1  
OUTPUT  
ENABLES  
OE2  
OE3  
10/95  
Motorola, Inc. 1995  
REV 7  

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