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MC74HC365ADT PDF预览

MC74HC365ADT

更新时间: 2024-11-27 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
6页 160K
描述
Hex 3-State Noninverting Buffer with Common Enables

MC74HC365ADT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP,
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.23
其他特性:WITH DUAL OUTPUT ENABLE系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:5 mm逻辑集成电路类型:BUS DRIVER
位数:6功能数量:1
端口数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):180 ns
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

MC74HC365ADT 数据手册

 浏览型号MC74HC365ADT的Datasheet PDF文件第2页浏览型号MC74HC365ADT的Datasheet PDF文件第3页浏览型号MC74HC365ADT的Datasheet PDF文件第4页浏览型号MC74HC365ADT的Datasheet PDF文件第5页浏览型号MC74HC365ADT的Datasheet PDF文件第6页 
SEMICONDUCTOR TECHNICAL DATA  
N SUFFIX  
PLASTIC PACKAGE  
16–LEAD  
High–Performance Silicon–Gate CMOS  
CASE 648–08  
The MC74HC365A is identical in pinout to the LS365. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
This device is a high–speed hex buffer with 3–state outputs and two  
common active–low Output Enables. When either of the enables is high, the  
buffer outputs are placed into high–impedance states. The HC365A has  
noninverting outputs.  
D SUFFIX  
SOIC PACKAGE  
16–LEAD  
CASE 751B–05  
DT SUFFIX  
TSSOP PACKAGE  
16–LEAD  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
CASE 948F–01  
ORDERING INFORMATION  
Low Input Current: 1 µA  
MC74HCXXXAN  
MC74HCXXXAD  
MC74HCXXXADT  
Plastic  
SOIC  
TSSOP  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
Chip Complexity: 90 FETs or 22.5 Equivalent Gates  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
OUTPUT  
1
2
16  
15  
V
CC  
OUTPUT  
ENABLE 2  
ENABLE 1  
2
3
5
7
A0  
A0  
A1  
A2  
A3  
A4  
A5  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y0  
A1  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
A5  
Y5  
A4  
Y4  
A3  
Y3  
4
Y1  
6
A2  
Y2  
10  
12  
14  
9
GND  
11  
13  
FUNCTION TABLE  
Inputs  
Output  
Y
1
OUTPUT ENABLE 1  
OUTPUT ENABLE 2  
PIN 16 = V  
PIN 8 = GND  
Enable Enable  
CC  
15  
1
2
A
L
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
X = don’t care  
Z = high impedance  
This document contains information on a new product. Specifications and information herein are subject to  
change without notice.  
3/97  
REV 0.1  
Motorola, Inc. 1997  

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