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MC74HC354DW PDF预览

MC74HC354DW

更新时间: 2024-11-27 22:36:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 解复用器锁存器逻辑集成电路光电二极管输入元件双倍数据速率
页数 文件大小 规格书
9页 210K
描述
8-Input Data Selector/Multiplexer With Data and Address Latches and 3-State Outputs

MC74HC354DW 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.56
Is Samacsys:N其他特性:TRANSPARENT ADDRESS/DATA LATCHES; 3 ENABLE INPUTS
系列:HC/UHJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:MULTIPLEXER
功能数量:1输入次数:8
输出次数:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):81 ns
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

MC74HC354DW 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
20  
20  
1
High–Performance Silicon–Gate CMOS  
The MC54/74HC354 is identical in pinout to the LS354. The device  
inputs are compatible with Standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
The HC354 selects one of eight latched binary Data Inputs, as deter-  
mined by the Address Inputs. The information at the Data Inputs is stored  
in the transparent 8–bit Data Latch when the Data–Latch Enable pin is  
held high. The Address information may be stored in the transparent  
Address Latch, which is enabled by the active–high Address–Enable pin.  
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
The device outputs are placed in high–impedance states when Output  
Enable 1 is high, Output Enable 2 is high, or Output Enable 3 is low.  
ORDERING INFORMATION  
MC54HCXXXJ  
MC74HCXXXN  
MC74HCXXXDW  
Ceramic  
Plastic  
SOIC  
The HC354 has a clocked Data Latch that is not transparent.  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2 to 6V  
Pinout: 20–Lead Package (Top View)  
Low Input Current: 1µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With the JEDEC Standard No. 7A Requirements  
Chip Complexity: 326 FETs or 81.5 Equivalent Gates  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
V
Y
Y
1
2
3
4
5
20  
19  
18  
17  
16  
CC  
LOGIC DIAGRAM  
OE3  
OE2  
OE1  
8
D0  
7
6
7
15  
D1  
6
D2  
8–BIT  
DATA  
LATCH  
(TRANS–  
PARENT)  
14 A0  
5
4
3
2
1
19  
18  
8–BIT  
MULTI–  
PLEXER  
3–STATE  
OUTPUT  
CONTROL  
3–STATE  
DATA  
OUTPUTS  
DATA  
INPUTS  
D3  
D4  
D5  
D6  
D7  
Y
Y
A1  
A2  
8
9
13  
12  
Data–Latch  
Enable  
Address–Latch  
Enable  
GND  
10  
11  
9
DATA–LATCH  
ENABLE  
14  
13  
12  
ADDRESS  
LATCH  
(TRANS–  
PARENT)  
A0  
ADDRESS  
INPUTS  
A1  
A2  
11  
PIN 20 = V  
CC  
PIN 10 = GND  
ADDRESS–LATCH  
ENABLE  
15  
16  
17  
OE1  
OUTPUT  
ENABLES  
OE2  
OE3  
10/95  
Motorola, Inc. 1995  
REV 7  

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