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MC74AC74DTR2 PDF预览

MC74AC74DTR2

更新时间: 2024-09-15 05:09:59
品牌 Logo 应用领域
安森美 - ONSEMI 触发器
页数 文件大小 规格书
12页 157K
描述
Dual D−Type Positive Edge−Triggered Flip−Flop

MC74AC74DTR2 数据手册

 浏览型号MC74AC74DTR2的Datasheet PDF文件第2页浏览型号MC74AC74DTR2的Datasheet PDF文件第3页浏览型号MC74AC74DTR2的Datasheet PDF文件第4页浏览型号MC74AC74DTR2的Datasheet PDF文件第5页浏览型号MC74AC74DTR2的Datasheet PDF文件第6页浏览型号MC74AC74DTR2的Datasheet PDF文件第7页 
MC74AC74, MC74ACT74  
Dual D−Type Positive  
Edge−Triggered Flip−Flop  
The MC74AC74/74ACT74 is a dual Dtype flipflop with  
Asynchronous Clear and Set inputs and complementary (Q,Q)  
outputs. Information at the input is transferred to the outputs on the  
positive edge of the clock pulse. Clock triggering occurs at a voltage  
level of the clock pulse and is not directly related to the transition time  
of the positive-going pulse. After the Clock Pulse input threshold  
voltage has been passed, the Data input is locked out and information  
present will not be transferred to the outputs until the next rising edge  
of the Clock Pulse input.  
http://onsemi.com  
PDIP14  
N SUFFIX  
CASE 646  
14  
1
Asynchronous Inputs:  
SOIC14  
D SUFFIX  
CASE 751A  
LOW input to S (Set) sets Q to HIGH level  
D
14  
LOW input to C (Clear) sets Q to LOW level  
D
1
Clear and Set are independent of clock  
Simultaneous LOW on C and S makes both Q and Q HIGH  
D
D
TSSOP14  
DT SUFFIX  
CASE 948G  
14  
Features  
1
Outputs Source/Sink 24 mA  
ACT74 Has TTL Compatible Inputs  
SOEIAJ14  
M SUFFIX  
CASE 965  
PbFree Packages are Available  
14  
1
V
C
D
CP  
S
Q
Q
2
CC  
D2  
2
2
D2  
2
14  
13  
12  
11  
10  
9
8
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
C
S
D1  
D2  
D
Q
CP  
Q
1
1
2
2
CP  
Q
D
Q
S
C
1
1
2
2
D1  
D2  
1
2
3
CP  
4
5
6
7
C
D
S
Q
Q
1
GND  
D1  
1
1
D1  
1
Figure 1. Pinout: 14Lead Packages Conductors  
(Top View)  
PIN ASSIGNMENT  
PIN  
D , D  
FUNCTION  
Data Inputs  
1
2
CP , CP  
Clock Pulse Inputs  
Direct Clear Inputs  
Direct Set Inputs  
Outputs  
1
2
C , C  
D1 D2  
S
, S  
D1 D2  
Q , Q , Q ,  
1
2
1
2
Q
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
October, 2006 Rev. 7  
MC74AC74/D  

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