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MC74AC823

更新时间： 2024-11-20 05:09:59
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 输出元件
页数 文件大小 规格书
8页 224K
描述
9-BIT REGISTER WITH 3-STATE OUTPUTS (Non-Inverting)

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MC74AC823 数据手册

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The MC74AC/ACT823 consists of nine D-type edge-triggered flip-flops. This  
device has 3-state outputs for bus systems, organized in a broadside pinning. In  
addition to the clock and output enabled pins, the buffered clock (CP) and buffered  
Output Enable (OE) are common to all flip-flips. The flip-flops will store the state of  
their individual D inputs that meet the setup and hold time requirements on the  
LOW-to-HIGH CPtransition. WithOE LOW, thecontentsoftheflip-flopsareavailable  
at the outputs. When OE is HIGH, the outputs go to the high impedance state.  
Operation of the OE input does not affect the state of the flip-flops. The  
MC74AC/ACT823 has Clear (CLR) and Clock Enable (EN) pins. These devices are  
ideal for parity bus interfacing in high performance systems.  
9-BIT REGISTER WITH  
3-STATE OUTPUTS  
When CLR is LOW, and OE is LOW, the outputs are LOW. When CLR is HIGH,  
data can be entered into the flip-flops. When EN is LOW, data on the inputs is  
transferred to the outputs on the LOW-to-HIGH clock transition. When EN is HIGH,  
the outputs do not change state, regardless of the data or clock input transitions.  
24  
1
N SUFFIX  
CASE 724-03  
• 3-State Outputs for Bus Interfacing  
PLASTIC PACKAGE  
• Broad Side Pin Configuration  
• ACT has TTL – Compatible Inputs  
• High Speed Parallel Positive Edge-Triggered D-Type Flip-Flops  
• High Performance Bus Interface Buffering for Busses Carrying Parity  
• Outputs Source/Sink 24 mA  
Pinout: 24-Lead Packages (Top View)  
V
O
O
O
O
O
O
O
O
O
8
EN  
14  
CP  
13  
CC  
24  
0
1
2
3
4
5
6
7
DW SUFFIX  
CASE 751E-04  
SOIC PACKAGE  
23  
22  
21  
20  
19  
18  
17  
16  
15  
PIN NAMES  
D
O
OE  
EN  
CLR  
CP  
– D  
– O  
8
Data Inputs  
Data Outputs  
Output Enable  
Clock Enable  
Clear  
0
0
8
1
2
3
4
5
6
7
8
9
10  
11  
12  
OE  
D
D
D
D
D
D
D
D
D
8
CLR GND  
1
0
1
2
3
4
5
6
7
FUNCTION TABLE  
Clock Input  
Inputs  
EN  
Internal  
Outputs  
O
Operating Mode  
OE  
CLR  
CP  
Dn  
Q
H
H
H
L
X
X
L
L
L
L
X
X
↑
↑
X
X
L
H
X
X
L
H
L
Z
Z
Z
L
High Z  
High Z  
Clear  
L
Clear  
H
L
H
H
H
H
X
X
X
X
NC  
NC  
Z
NC  
Hold  
Hold  
H
H
H
H
L
L
↑
↑
L
H
L
H
Z
Z
Load  
Load  
L
L
H
H
L
L
↑
↑
L
H
L
H
L
H
Load  
Load  
H = HIGH Voltage Level; L = LOW Voltage Level; X = Immaterial; Z = High Impedance State; ↑ = LOW-to-High Transition; NC = No Change  
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  
FACT DATA  
5-1  
12345678

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