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MC74AC823DW PDF预览

MC74AC823DW

更新时间： 2024-11-08 23:01:31
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 输出元件
页数 文件大小 规格书
8页 223K
描述
9-BIT REGISTER WITH 3-STATE OUTPUTS

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中文翻译

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MC74AC823DW 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP,
针数：24Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.92
系列：ACJESD-30 代码：R-PDSO-G24
JESD-609代码：e0长度：15.4 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.024 A位数：9
功能数量：1端口数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP24,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3/5 V
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：FF/Latches最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：7.5 mm
Base Number Matches：1

MC74AC823DW 数据手册

 浏览型号MC74AC823DW的Datasheet PDF文件第2页浏览型号MC74AC823DW的Datasheet PDF文件第3页浏览型号MC74AC823DW的Datasheet PDF文件第4页浏览型号MC74AC823DW的Datasheet PDF文件第5页浏览型号MC74AC823DW的Datasheet PDF文件第6页浏览型号MC74AC823DW的Datasheet PDF文件第7页 
Product Preview  
The MC74AC/ACT823 consists of nine D-type edge-triggered flip-flops. This  
device has 3-state outputs for bus systems, organized in a broadside pinning. In  
addition to the clock and output enabled pins, the buffered clock (CP) and buffered  
Output Enable (OE) are common to all flip-flips. The flip-flops will store the state of  
their individual D inputs that meet the setup and hold time requirements on the  
LOW-to-HIGH CPtransition. WithOE LOW, thecontentsoftheflip-flopsareavailable  
at the outputs. When OE is HIGH, the outputs go to the high impedance state.  
Operation of the OE input does not affect the state of the flip-flops. The  
MC74AC/ACT823 has Clear (CLR) and Clock Enable (EN) pins. These devices are  
ideal for parity bus interfacing in high performance systems.  
9-BIT REGISTER WITH  
3-STATE OUTPUTS  
When CLR is LOW, and OE is LOW, the outputs are LOW. When CLR is HIGH,  
data can be entered into the flip-flops. When EN is LOW, data on the inputs is  
transferred to the outputs on the LOW-to-HIGH clock transition. When EN is HIGH,  
the outputs do not change state, regardless of the data or clock input transitions.  
24  
1
N SUFFIX  
CASE 724-03  
• 3-State Outputs for Bus Interfacing  
PLASTIC PACKAGE  
• Broad Side Pin Configuration  
• ACT has TTL – Compatible Inputs  
• High Speed Parallel Positive Edge-Triggered D-Type Flip-Flops  
• High Performance Bus Interface Buffering for Busses Carrying Parity  
• Outputs Source/Sink 24 mA  
Pinout: 24-Lead Packages (Top View)  
V
O
O
O
O
O
O
O
O
O
8
EN  
14  
CP  
13  
CC  
24  
0
1
2
3
4
5
6
7
DW SUFFIX  
CASE 751E-04  
SOIC PACKAGE  
23  
22  
21  
20  
19  
18  
17  
16  
15  
PIN NAMES  
D
O
OE  
EN  
CLR  
CP  
– D  
– O  
8
Data Inputs  
Data Outputs  
Output Enable  
Clock Enable  
Clear  
0
0
8
1
2
3
4
5
6
7
8
9
10  
11  
12  
OE  
D
D
D
D
D
D
D
D
D
8
CLR GND  
1
0
1
2
3
4
5
6
7
FUNCTION TABLE  
Clock Input  
Inputs  
EN  
Internal  
Outputs  
O
Operating Mode  
OE  
CLR  
CP  
Dn  
Q
H
H
H
L
X
X
L
L
L
L
X
X
↑
↑
X
X
L
H
X
X
L
H
L
Z
Z
Z
L
High Z  
High Z  
Clear  
L
Clear  
H
L
H
H
H
H
X
X
X
X
NC  
NC  
Z
NC  
Hold  
Hold  
H
H
H
H
L
L
↑
↑
L
H
L
H
Z
Z
Load  
Load  
L
L
H
H
L
L
↑
↑
L
H
L
H
L
H
Load  
Load  
H = HIGH Voltage Level; L = LOW Voltage Level; X = Immaterial; Z = High Impedance State; ↑ = LOW-to-High Transition; NC = No Change  
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  
FACT DATA  
5-1  
12345678

中文翻译

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