Table of Contents
Paragraph
Number
Title
Page
Number
4.6
Bus Arbitration .......................................................................................4-49
Bus Request ..........................................................................................4-52
Bus Grant...............................................................................................4-53
Bus Grant Acknowledge ........................................................................4-53
Bus Arbitration Control...........................................................................4-54
Slave (Disable CPU32+) Mode Bus Arbitration .....................................4-55
Slave (Disable CPU32+) Mode Bus Exceptions ....................................4-59
HALT......................................................................................................4-59
RETRY...................................................................................................4-59
Internal Accesses...................................................................................4-59
Show Cycles ..........................................................................................4-62
Reset Operation.....................................................................................4-63
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.6.6.1
4.6.6.2
4.6.7
4.6.8
4.7
Section 5
CPU32+
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.1.1
5.3.1.2
5.3.1.3
5.3.1.4
5.3.2
Overview..................................................................................................5-1
Features...................................................................................................5-2
Loop Mode Instruction Execution.............................................................5-3
Vector Base Register...............................................................................5-4
Exception Handling..................................................................................5-4
Addressing Modes ...................................................................................5-5
Architecture Summary .............................................................................5-5
Programming Model.................................................................................5-6
Registers..................................................................................................5-7
Instruction Set..........................................................................................5-8
M68000 Family Compatibility.................................................................5-10
New Instructions. ...................................................................................5-10
Low-Power Stop (LPSTOP)...................................................................5-10
Table Lookup and Interpolate (TBL). .....................................................5-10
Unimplemented Instructions. .................................................................5-10
Instruction Format and Notation.............................................................5-10
Instruction Summary..............................................................................5-13
Condition Code Register........................................................................5-17
Data Movement Instructions ..................................................................5-19
Integer Arithmetic Operations ................................................................5-19
Logic Instructions...................................................................................5-21
Shift and Rotate Instructions..................................................................5-22
Bit Manipulation Instructions..................................................................5-23
Binary-Coded Decimal (BCD) Instructions.............................................5-24
Program Control Instructions .................................................................5-24
System Control Instructions...................................................................5-25
Condition Tests......................................................................................5-26
Using the TBL Instructions.....................................................................5-27
Table Example 1: Standard Usage........................................................5-28
Table Example 2: Compressed Table....................................................5-29
5.3.3
5.3.3.1
5.3.3.2
5.3.3.3
5.3.3.4
5.3.3.5
5.3.3.6
5.3.3.7
5.3.3.8
5.3.3.9
5.3.3.10
5.3.4
5.3.4.1
5.3.4.2
iv
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