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MC68MH360EM33L PDF预览

MC68MH360EM33L

更新时间: 2024-01-24 01:26:17
品牌 Logo 应用领域
恩智浦 - NXP 通信时钟局域网数据传输外围集成电路
页数 文件大小 规格书
3页 269K
描述
4 CHANNEL(S), 10Mbps, LOCAL AREA NETWORK CONTROLLER, PQFP240, PLASTIC, QFP-240

MC68MH360EM33L 技术参数

生命周期:Transferred包装说明:FQFP,
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.73地址总线宽度:32
边界扫描:YES总线兼容性:68000
最大时钟频率:33.34 MHz通信协议:ASYNC, BIT; SYNC, BYTE; SYNC, HDLC; SYNC, SDLC; BISYNC
数据编码/解码方法:NRZ; NRZI; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER); DIFF BIPH-LEVEL最大数据传输速率:1.25 MBps
外部数据总线宽度:32JESD-30 代码:S-PQFP-G240
长度:31.305 mm低功率模式:YES
串行 I/O 数:4端子数量:240
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装形状:SQUARE封装形式:FLATPACK, FINE PITCH
认证状态:Not Qualified座面最大高度:4.15 mm
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:HCMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:31.305 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LANBase Number Matches:1

MC68MH360EM33L 数据手册

 浏览型号MC68MH360EM33L的Datasheet PDF文件第2页浏览型号MC68MH360EM33L的Datasheet PDF文件第3页 
Freescale Semiconductor, Inc.  
MC68360  
Preliminary Information  
MC68360 New Features on REV C.1  
March 7, 1995  
Some new features have been added to the XC68360 Revision C.1 device. The uses of these new  
features are not required with an exception of hardware device errata fixes. The main purpose of the revision  
C.1 device is to fix the errata items that is described on the QUICC Device Errata as "will be fixed on rev C.1".  
Revision C.1 device is visually marked with mask number 1E68C. The RISC revision number in the XC68360  
at address (MiscBase+$00) has the value $0003.  
NOTE  
The following information is not described in the MC68360 User's Manual  
(MC68360UM/AD). The use of this document along with the QUICC Device  
Errata, QUICC Users Manual Errata, Changes in Rev B, the Centronics  
Controller Manual and the User's Manual will fully describe revision C.1  
device operation. All of this information will be incorporated into a future  
revision of the User’s Manual.  
CPM  
DUAL PORT RAM  
256 Bytes of memory have been added to the internal RAM of the part. The memory map on page 3-3 of the  
User’s Manual should now reflect that the area from DPRBASE + $700 to DPRBASE + $7FF now contains  
256 bytes of memory in Dual-Port RAM which contains User Data / BDs / Microcode Scratch.  
NOTE  
This extra memory will not be available if a RAM microcode package is  
installed in the QUICC.  
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice.  
©
Freescale Semiconductor,  
1995  
IncF. or More Information On This Product,  
Go to: www.freescale.com  

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