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MC68MH360RC25L PDF预览

MC68MH360RC25L

更新时间: 2024-01-17 04:31:34
品牌 Logo 应用领域
恩智浦 - NXP 通信时钟局域网数据传输外围集成电路
页数 文件大小 规格书
14页 319K
描述
4 CHANNEL(S), 10Mbps, LOCAL AREA NETWORK CONTROLLER, CPGA241, PGA-241

MC68MH360RC25L 技术参数

生命周期:Transferred包装说明:PGA,
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.73地址总线宽度:32
边界扫描:YES总线兼容性:68000
最大时钟频率:25 MHz通信协议:ASYNC, BIT; SYNC, BYTE; SYNC, HDLC; SYNC, SDLC; BISYNC
数据编码/解码方法:NRZ; NRZI; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER); DIFF BIPH-LEVEL最大数据传输速率:1.25 MBps
外部数据总线宽度:32JESD-30 代码:S-CPGA-P241
长度:47.245 mm低功率模式:YES
串行 I/O 数:4端子数量:241
最高工作温度:70 °C最低工作温度:
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装形状:SQUARE封装形式:GRID ARRAY
认证状态:Not Qualified最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:NO技术:HCMOS
温度等级:COMMERCIAL端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
宽度:47.245 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches:1

MC68MH360RC25L 数据手册

 浏览型号MC68MH360RC25L的Datasheet PDF文件第2页浏览型号MC68MH360RC25L的Datasheet PDF文件第3页浏览型号MC68MH360RC25L的Datasheet PDF文件第4页浏览型号MC68MH360RC25L的Datasheet PDF文件第5页浏览型号MC68MH360RC25L的Datasheet PDF文件第6页浏览型号MC68MH360RC25L的Datasheet PDF文件第7页 
Freescale Semiconductor  
Order this document  
by MC68360D  
MC68360  
Product Brief  
MC68360 QUad Integrated Communication  
Controller (QUICC  
)
INTRODUCTION  
The MC68360 QUad Integrated Communication Controller (QUICC) is a versatile one-chip integrated  
microprocessor and peripheral combination that can be used in a variety of controller applications. It  
particularly excels in communications activities. The QUICC (pronounced “quick”) can be described as a  
next-generation MC68302 with higher performance in all areas of device operation, increased flexibility,  
major extensions in capability, and higher integration. The term "quad" comes from the fact that there are  
four serial communications controllers (SCCs) on the device; however, there are actually seven serial  
channels: four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI).  
QUICC Key Features  
The following list summarizes the key MC68360 QUICC features:  
• CPU32+ Processor (4.5 MIPS at 25 MHz)  
— 32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32)  
— Background Debug Mode  
— Byte-Misaligned Addressing  
• Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)  
• Up to 32 Address Lines (At Least 28 Always Available)  
• Complete Static Design (0–25-MHz Operation)  
• Slave Mode To Disable CPU32+ (Allows Use with External Processors)  
— Multiple QUICCs Can Share One System Bus (One Master)  
— MC68040 Companion Mode Allows QUICC To Be an MC68040 Companion  
For More Information On This Product,  
Go to: www.freescale.com  

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