Table of Contents
Paragraph
Number
Title
Page
Number
2.1.7.5
2.1.7.6
2.1.7.7
2.1.7.8
2.1.8
2.1.8.1
2.1.8.2
2.1.8.3
2.1.8.4
2.1.8.5
Transfer Size (SIZ1, SIZ0).......................................................................2-8
Read/Write (R/W).....................................................................................2-8
Output Enable/Address Multiplex (OE/AMUX).........................................2-9
Byte Write Enable (WE3–WE0). ..............................................................2-9
Bus Arbitration Signals.............................................................................2-9
Bus Request (BR)....................................................................................2-9
Bus Grant (BG). .......................................................................................2-9
Bus Grant Acknowledge (BGACK). .........................................................2-9
Read-Modify-Write Cycle/Initial Configuration (RMC/CONFIG0).............2-9
Bus Clear Out/Initial Configuration/Row Address Select Double-Drive (BCL-
RO/CONFIG1/RAS2DD).2-9
2.1.9
System Control Signals..........................................................................2-10
2.1.9.1
2.1.9.2
2.1.9.3
2.1.9.4
2.1.10
2.1.10.1
2.1.10.2
2.1.10.3
2.1.10.4
2.1.11
2.1.11.1
2.1.11.2
2.1.11.3
2.1.11.4
2.1.11.5
2.1.12
2.1.12.1
2.1.12.2
2.1.12.3
2.1.12.4
2.1.12.5
2.1.12.6
2.1.13
Soft Reset (RESETS). ...........................................................................2-10
Hard Reset (RESETH)...........................................................................2-10
Halt (HALT)............................................................................................2-10
Bus Error (BERR). .................................................................................2-10
Clock Signals .........................................................................................2-10
System Clock Outputs (CLKO2–CLKO1). .............................................2-10
Crystal Oscillator (EXTAL, XTAL)..........................................................2-11
External Filter Capacitor (XFC)..............................................................2-11
Clock Mode Select (MODCK1–MODCK0).............................................2-11
Instrumentation and Emulation Signals .................................................2-11
Instruction Fetch/Development Serial Input (IFETCH/DSI)....................2-11
Instruction Pipe/Development Serial Output (IPIPE0/DSO)...................2-11
Instruction Pipe/Row Address Select Double-Drive (IPIPE1/RAS1DD).2-11
Breakpoint/Development Serial clock (BKPT/DSCLK). .........................2-11
Freeze/Initial Configuration (FREEZE/CONFIG2). ................................2-12
Test Signals ...........................................................................................2-12
TRI-State Signal (TRIS).........................................................................2-12
Test Reset (TRST).................................................................................2-12
Test Clock (TCK). ..................................................................................2-12
Test Mode Select (TMS)........................................................................2-12
Test Data In (TDI). .................................................................................2-12
Test Data Out (TDO)..............................................................................2-12
Initial Configuration Pins (CONFIG).......................................................2-12
Power Signals........................................................................................2-13
VCCSYN and GNDSYN.........................................................................2-13
VCCCLK and GNDCLK. ........................................................................2-13
GNDS1 and GNDS2. .............................................................................2-13
VCC and GND. ......................................................................................2-13
NC4–NC1...............................................................................................2-13
System Bus Signal Index in Slave Mode ...............................................2-14
On-Chip Peripherals Signal Index..........................................................2-15
2.1.14
2.1.14.1
2.1.14.2
2.1.14.3
2.1.14.4
2.1.14.5
2.2
2.3
Section 3
ii
MC68360 USER’S MANUAL
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