Table of Contents
Paragraph
Number
Title
Page
Number
Section 1
Introduction
1.1
1.2
QUICC Key Features .............................................................................. 1-1
QUICC Architecture Overview................................................................. 1-4
CPU32+ Core.......................................................................................... 1-5
System Integration Module (SIM60)........................................................ 1-5
Communications Processor Module (CPM) ............................................ 1-6
Upgrading Designs from the MC68302................................................... 1-6
Architectural Approach............................................................................ 1-6
Hardware Compatibility Issues................................................................ 1-7
Software Compatibility Issues ................................................................. 1-7
QUICC Glueless System Design............................................................. 1-8
QUICC Serial Configurations .................................................................. 1-9
QUICC Serial Configuration Examples ................................................. 1-16
QUICC System Bus Configurations ...................................................... 1-17
1.2.1
1.2.2
1.2.3
1.3
1.3.1
1.3.2
1.3.3
1.4
1.5
1.6
1.7
Section 2
Signal Descriptions
2.1
2.1.1
2.1.1.1
2.1.1.2
2.1.2
System Bus Signal Index ........................................................................ 2-1
Address Bus............................................................................................ 2-1
Address Bus (A27–A0)............................................................................ 2-1
Address Bus (A31–A28).......................................................................... 2-1
Function Codes (FC3–FC0) .................................................................... 2-5
Data Bus.................................................................................................. 2-5
Data Bus (D31–D16)............................................................................... 2-5
Data Bus (D15–D0)................................................................................. 2-6
Parity ....................................................................................................... 2-6
Parity (PRTY0). ....................................................................................... 2-6
Parity (PRTY1). ....................................................................................... 2-6
Parity (PRTY2). ....................................................................................... 2-6
Parity (PRTY3). ....................................................................................... 2-6
Memory Controller................................................................................... 2-6
Chip Select/Row Address Select (CS6–CS0/RAS6–RAS0) ................... 2-6
Chip Select/Row Address Select/Interrupt Acknowledge (CS7/RAS7/IACK7).
2.1.3
2.1.3.1
2.1.3.2
2.1.4
2.1.4.1
2.1.4.2
2.1.4.3
2.1.4.4
2.1.5
2.1.5.1
2.1.5.2
2-6
2.1.5.3
1).
Column Address Select/Interrupt Acknowledge (CAS3–CAS0/IACK6, 3, 2,
2-7
2.1.5.4
2.1.6
2.1.7
2.1.7.1
2.1.7.2
2.1.7.3
2.1.7.4
Address Multiplex (AMUX). ..................................................................... 2-7
Interrupt Request Level (IRQ7–IRQ1)..................................................... 2-7
Bus Control Signals................................................................................. 2-7
Data and Size Acknowledge (DSACK1–DSACK0). ................................ 2-8
Autovector/Interrupt Acknowledge (AVEC/IACK5).................................. 2-8
Address Strobe (AS). .............................................................................. 2-8
Data Strobe (DS)..................................................................................... 2-8
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