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MC54HC4051J PDF预览

MC54HC4051J

更新时间： 2024-11-15 00:01:07
品牌 Logo 应用领域
安森美 - ONSEMI 解复用器
页数 文件大小 规格书
15页 454K
描述
Analog Multiplexers/Demultiplexers

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MC54HC4051J 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.23
模拟集成电路 - 其他类型：SINGLE-ENDED MULTIPLEXERJESD-30 代码：R-GDIP-T16
JESD-609代码：e0长度：19.495 mm
负电源电压最大值（Vsup）：-6 V负电源电压最小值（Vsup）：-1 V
标称负供电电压 (Vsup)：-4.5 V信道数量：8
功能数量：1端子数量：16
标称断态隔离度：50 dB通态电阻匹配规范：18 Ω
最大通态电阻 (Ron)：170 Ω最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2/6,GND/-6 V
认证状态：Not Qualified座面最大高度：5.08 mm
最大信号电流：0.025 A子类别：Multiplexer or Switches
最大供电电流 (Isup)：0.16 mA最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：1 V标称供电电压 (Vsup)：4.5 V
表面贴装：NO切换：BREAK-BEFORE-MAKE
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

MC54HC4051J 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
The MC54/74HC4051, MC74HC4052 and MC54/74HC4053 utilize sili-  
con–gate CMOS technology to achieve fast propagation delays, low ON  
resistances, and low OFF leakage currents. These analog multiplexers/  
demultiplexers control analog voltages that may vary across the complete  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
power supply range (from V  
to V ).  
CC  
EE  
16  
16  
The HC4051, HC4052 and HC4053 are identical in pinout to the  
metal–gate MC14051B, MC14052B and MC14053B. The Channel–Select  
inputs determine which one of the Analog Inputs/Outputs is to be connected,  
by means of an analog switch, to the Common Output/Input. When the  
Enable pin is HIGH, all analog switches are turned off.  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
The Channel–Select and Enable inputs are compatible with standard  
CMOS outputs; with pullup resistors they are compatible with LSTTL  
outputs.  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
These devices have been designed so that the ON resistance (R ) is  
on  
of metal–gate CMOS analog  
1
more linear over input voltage than R  
switches.  
on  
DW SUFFIX  
SOIC PACKAGE  
CASE 751G–02  
16  
16  
For multiplexers/demultiplexers with channel–select latches, see  
HC4351, HC4352 and HC4353.  
1
1
•
•
•
•
•
•
Fast Switching and Propagation Speeds  
Low Crosstalk Between Switches  
Diode Protection on All Inputs/Outputs  
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
Analog Power Supply Range (V  
– V ) = 2.0 to 12.0 V  
CC  
EE  
ORDERING INFORMATION  
Digital (Control) Power Supply Range (V  
CC  
Improved Linearity and Lower ON Resistance Than Metal–Gate  
– GND) = 2.0 to 6.0 V  
MC54HCXXXXJ  
Ceramic  
Plastic  
SOIC  
SOIC Wide  
TSSOP  
MC74HCXXXXN  
MC74HCXXXXD  
MC74HCXXXXDW  
MC74HCXXXXDT  
Counterparts  
•
•
•
Low Noise  
In Compliance With the Requirements of JEDEC Standard No. 7A  
Chip Complexity: HC4051 — 184 FETs or 46 Equivalent Gates  
HC4052 — 168 FETs or 42 Equivalent Gates  
HC4053 — 156 FETs or 39 Equivalent Gates  
FUNCTION TABLE – MC54/74HC4051  
Control Inputs  
LOGIC DIAGRAM  
MC54/74HC4051  
Select  
Single–Pole, 8–Position Plus Common Off  
Enable  
C
B
A
ON Channels  
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
X0  
X1  
X2  
X3  
X4  
X5  
X6  
X7  
NONE  
13  
X0  
14  
X1  
L
15  
X2  
H
H
H
H
X
ANALOG  
12  
1
MULTIPLEXER/  
DEMULTIPLEXER  
X3  
X4  
X5  
X6  
X7  
A
3
COMMON  
OUTPUT/  
INPUT  
L
INPUTS/  
X
V
OUTPUTS  
H
H
X
5
2
4
X = Don’t Care  
Pinout: MC54/74HC4051 (Top View)  
11  
10  
9
X2  
X1  
X0  
X3  
A
B
C
9
CC  
CHANNEL  
SELECT  
INPUTS  
B
16  
15  
14  
13  
12  
11  
10  
C
6
ENABLE  
PIN 16 = V  
CC  
PIN 7 = V  
EE  
PIN 8 = GND  
1
2
3
4
5
6
7
8
X4  
X6  
X
X7  
X5 Enable  
V
GND  
EE  
10/95  
Motorola, Inc. 1995  
REV 7  
1234567...15

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