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MC54HC4060AJ PDF预览

MC54HC4060AJ

更新时间: 2024-11-15 00:01:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 振荡器计数器触发器逻辑集成电路输出元件输入元件
页数 文件大小 规格书
12页 136K
描述
14-Stage Binary Ripple Counter With Oscillator

MC54HC4060AJ 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.69
Is Samacsys:N其他特性:OUTPUTS FROM 10 STAGES AVAILABLE; BUILT-IN OSCILLATOR; OSCILLATOR DISABLED BY CLEAR INPUT
计数方向:UP系列:HC/UH
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.495 mm负载电容(CL):50 pF
负载/预设输入:NO逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:12000000 Hz最大I(ol):0.0024 A
工作模式:ASYNCHRONOUS位数:14
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):300 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Counters最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:7.62 mm
最小 fmax:25 MHzBase Number Matches:1

MC54HC4060AJ 数据手册

 浏览型号MC54HC4060AJ的Datasheet PDF文件第2页浏览型号MC54HC4060AJ的Datasheet PDF文件第3页浏览型号MC54HC4060AJ的Datasheet PDF文件第4页浏览型号MC54HC4060AJ的Datasheet PDF文件第5页浏览型号MC54HC4060AJ的Datasheet PDF文件第6页浏览型号MC54HC4060AJ的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
16  
The MC54/74C4060A is identical in pinout to the standard CMOS  
MC14060B. The device inputs are compatible with standard CMOS out-  
puts; with pullup resistors, they are compatible with LSTTL outputs.  
This device consists of 14 master–slave flip–flops and an oscillator  
with a frequency that is controlled either by a crystal or by an RC circuit  
connected externally. The output of each flip–flop feeds the next and the  
frequency at each output is half of that of the preceding one. The state of  
the counter advances on the negative–going edge of the Osc In. The  
active–high Reset is asynchronous and disables the oscillator to allow  
very low power consumption during stand–by operation.  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
State changes of the Q outputs do not occur simultaneously because  
of internal ripple delays. Therefore, decoded output signals are subject to  
decoding spikes and may have to be gated with Osc Out 2 of the  
HC4060A.  
16  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
DT SUFFIX  
TSSOP PACKAGE  
CASE 748C–03  
16  
1
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With JEDEC Standard No. 7A Requirements  
Chip Complexity: 390 FETs or 97.5 Equivalent Gates  
ORDERING INFORMATION  
MC54HCXXXXAJ  
MC74HCXXXXAN  
MC74HCXXXXAD  
Ceramic  
Plastic  
SOIC  
MC74HCXXXXADT TSSOP  
LOGIC DIAGRAM  
Osc Out 1 Osc Out 2  
FUNCTION TABLE  
10  
9
Clock  
Reset  
Output State  
7
5
L
L
No Charge  
Q4  
Advance to Next State  
All Outputs Are Low  
Q5  
4
11  
X
H
Q6  
Osc In  
6
Q7  
14  
13  
15  
1
Pinout: 16–Lead Plastic Package (Top View)  
Q8  
Q9  
Osc  
Out 1 Out 2  
Q9 Reset Osc In  
Osc  
V
Q10  
15  
Q8  
14  
Q10  
Q12  
Q13  
Q14  
CC  
16  
13  
12  
11  
10  
9
2
3
12  
Pin 16 = V  
Pin 8 = GND  
CC  
Reset  
1
2
3
4
5
6
7
8
GND  
Q12  
Q13  
Q14  
Q6  
Q5  
Q7  
Q4  
3/96  
REV 1  
Motorola, Inc. 1996  

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