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MC54HC4353J PDF预览

MC54HC4353J

更新时间： 2024-11-14 22:36:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 解复用器
页数 文件大小 规格书
13页 480K
描述
Analog Multipexers/Demultiplexers with Address Latch

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中文翻译

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MC54HC4353J 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP20,.3
针数：20Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.92
模拟集成电路 - 其他类型：DIFFERENTIAL MULTIPLEXERJESD-30 代码：R-CDIP-T20
JESD-609代码：e0长度：24.515 mm
标称负供电电压 (Vsup)：-6 V信道数量：2
功能数量：3端子数量：20
标称断态隔离度：40 dB通态电阻匹配规范：10 Ω
最大通态电阻 (Ron)：100 Ω最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装等效代码：DIP20,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2/12 V
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Multiplexer or Switches最大供电电流 (Isup)：0.16 mA
标称供电电压 (Vsup)：6 V表面贴装：NO
最长断开时间：49 ns最长接通时间：59 ns
切换：BREAK-BEFORE-MAKE技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

MC54HC4353J 数据手册

 浏览型号MC54HC4353J的Datasheet PDF文件第2页浏览型号MC54HC4353J的Datasheet PDF文件第3页浏览型号MC54HC4353J的Datasheet PDF文件第4页浏览型号MC54HC4353J的Datasheet PDF文件第5页浏览型号MC54HC4353J的Datasheet PDF文件第6页浏览型号MC54HC4353J的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
The MC54/74HC4351, and MC54/74HC4353 utilize silicon–gate CMOS  
technology to achieve fast propagation delays, low ON resistances, and low  
OFF leakage currents. These analog multiplexers/demultiplexers control  
analog voltages that may vary across the complete power supply range  
20  
20  
1
(from V  
to V ).  
CC  
EE  
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
The Channel–Select inputs determine which one of the Analog Inputs/  
Outputs is to be connected, by means of an analog switch, to the Common  
Output/Input. The data at the Channel–Select inputs may be latched by  
using the active–low Latch Enable pin. When Latch Enable is high, the latch  
is transparent. When either Enable 1 (active low) or Enable 2 (active high) is  
inactive, all analog switches are turned off.  
1
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
The Channel–Select and Enable inputs are compatible with standard  
CMOS outputs; with pullup resistors, they are compatible with LSTTL  
outputs.  
ORDERING INFORMATION  
These devices have been designed so that the ON resistance (R ) is  
on  
of metal–gate CMOS analog  
MC54HCXXXXJ  
MC74HCXXXXN  
MC74HCXXXXDW  
Ceramic  
Plastic  
SOIC  
more linear over input voltage than R  
switches.  
on  
For multiplexers/demultiplexers without latches, see the HC4051,  
HC4052, and HC4053.  
•
•
•
•
•
•
•
•
Fast Switching and Propagation Speeds  
Low Crosstalk Between Switches  
Diode Protection on All Inputs/Outputs  
PIN ASSIGNMENT  
MC54/74HC4351  
Analog Power Supply Range (V  
CC  
– V ) = 2.0 to 12.0 V  
EE  
X4  
1
20  
V
CC  
Digital (Control) Power Supply Range (V  
Improved Linearity and Lower ON Resistance than Metal–Gate Types  
Low Noise  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
Chip Complexity: HC4351 — 222 FETs or 55.5 Equivalent Gates  
HC4353 — 186 FETs or 46.5 Equivalent Gates  
– GND) = 2.0 to 6.0 V  
CC  
X6  
NC  
X
2
3
4
19  
18  
17  
X2  
X1  
X0  
X7  
X5  
5
6
7
16  
15  
14  
X3  
A
•
ENABLE 1  
ENABLE 2  
NC  
8
13  
12  
11  
B
C
V
9
EE  
GND  
LATCH  
ENABLE  
10  
NC = NO CONNECTION  
10/95  
Motorola, Inc. 1995  
REV 6  
1234567...13

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