MC14553

更新时间： 2024-11-09 22:58:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		计数器
页数	文件大小	规格书
8页	235K
描述
3-Digit BCD Counter

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中文翻译

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数据手册

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MC14553 数据手册

SEMICONDUCTOR TECHNICAL DATA

L SUFFIX

CERAMIC

CASE 620

The MC14553B 3–digit BCD counter consists of 3 negative edge triggered

BCD counters that are cascaded synchronously. A quad latch at the output

of each counter permits storage of any given count. The information is then

time division multiplexed, providing one BCD number or digit at a time. Digit

select outputs provide display control. All outputs are TTL compatible.

An on–chip oscillator provides the low–frequency scanning clock which

drives the multiplexer output selector.

P SUFFIX

PLASTIC

CASE 648

This device is used in instrumentation counters, clock displays, digital

panel meters, and as a building block for general logic applications.

DW SUFFIX

SOIC

CASE 751G

•

TTL Compatible Outputs

On–Chip Oscillator

Cascadable

Clock Disable Input

Pulse Shaping Permits Very Slow Rise Times on Input Clock

Output Latches

Master Reset

ORDERING INFORMATION

MC14XXXBCP

MC14XXXBCL

MC14XXXBDW

Plastic

Ceramic

SOIC

= – 55° to 125°C for all packages.

MAXIMUM RATINGS* (Voltages Referenced to V

)

Symbol

Parameter

DC Supply Voltage

Value

Unit

BLOCK DIAGRAM

– 0.5 to + 18.0

V , V

Input or Output Voltage (DC or Transient)

Input Current (DC or Transient), per Pin

Output Current (DC or Transient), per Pin

Power Dissipation, per Package†

Storage Temperature

– 0.5 to V

+ 0.5

in out

± 10

CIA

CIB

+ 20

500

out

CLOCK

stg

– 65 to + 150

260

O.F.

DS1

DS2

DS3

Lead Temperature (8–Second Soldering)

DIS

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C

= PIN 16

= PIN 8

TRUTH TABLE

Inputs

Master

This device contains protection circuitry to

guard against damage due to high static

voltages or electric fields. However, pre-

cautions must be taken to avoid applications of

any voltage higher than maximum rated volt-

ages to this high–impedance circuit. For proper

Reset

Clock

Disable

Outputs

No Change

Advance

No Change

Advance

No Change

Latched

operation, V and V

should be constrained

in out

to the range V

(V or V

)

SS in out

Unused inputs must always be tied to an

appropriate logic voltage level (e.g., either V

or V ). Unused outputs must be left open.

Latched

Q0 = Q1 = Q2 = Q3 = 0

X = Don’t Care

REV 3

1/94

Motorola, Inc. 1995

MOTOROLA CMOS LOGIC DATA

MC14553B

12 3 4 5 6 7 8

中文翻译

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与MC14553相关器件

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MC145532	MOTOROLA	获取价格	ADPCM Transcoder
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MC145532DWR2	MOTOROLA	获取价格	A/MU-LAW, ADPCM CODEC, PDSO16, SOG-16
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MC145537EVK	MOTOROLA	获取价格	MC14LC5540 ADPCM Codec Evaluation Kit
MC14553B	MOTOROLA	获取价格	3-Digit BCD Counter
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MC14553B_06	ONSEMI	获取价格	3−Digit BCD Counter
MC14553BALD	MOTOROLA	获取价格	暂无描述

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