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MC14553B

更新时间： 2024-11-28 22:58:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器
页数 文件大小 规格书
8页 235K
描述
3-Digit BCD Counter

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中文翻译

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MC14553B 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 620  
The MC14553B 3–digit BCD counter consists of 3 negative edge triggered  
BCD counters that are cascaded synchronously. A quad latch at the output  
of each counter permits storage of any given count. The information is then  
time division multiplexed, providing one BCD number or digit at a time. Digit  
select outputs provide display control. All outputs are TTL compatible.  
An on–chip oscillator provides the low–frequency scanning clock which  
drives the multiplexer output selector.  
P SUFFIX  
PLASTIC  
CASE 648  
This device is used in instrumentation counters, clock displays, digital  
panel meters, and as a building block for general logic applications.  
DW SUFFIX  
SOIC  
CASE 751G  
•
•
•
•
•
•
•
TTL Compatible Outputs  
On–Chip Oscillator  
Cascadable  
Clock Disable Input  
Pulse Shaping Permits Very Slow Rise Times on Input Clock  
Output Latches  
Master Reset  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBDW  
Plastic  
Ceramic  
SOIC  
T
A
= – 55° to 125°C for all packages.  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
BLOCK DIAGRAM  
V
DD  
– 0.5 to + 18.0  
4
3
V , V  
Input or Output Voltage (DC or Transient)  
Input Current (DC or Transient), per Pin  
Output Current (DC or Transient), per Pin  
Power Dissipation, per Package†  
Storage Temperature  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
I
in  
± 10  
mA  
mA  
mW  
C
CIA  
CIB  
9
7
6
Q0  
Q1  
Q2  
I
+ 20  
500  
out  
CLOCK  
12  
10  
P
D
LE  
T
stg  
– 65 to + 150  
260  
5
Q3  
O.F.  
DS1  
DS2  
DS3  
T
L
Lead Temperature (8–Second Soldering)  
C
14  
2
11  
13  
DIS  
MR  
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
1
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
15  
V
V
= PIN 16  
= PIN 8  
DD  
SS  
TRUTH TABLE  
Inputs  
Master  
This device contains protection circuitry to  
guard against damage due to high static  
voltages or electric fields. However, pre-  
cautions must be taken to avoid applications of  
any voltage higher than maximum rated volt-  
ages to this high–impedance circuit. For proper  
Reset  
Clock  
Disable  
LE  
Outputs  
0
0
0
0
0
0
0
0
1
0
0
1
0
0
X
0
0
X
No Change  
Advance  
No Change  
Advance  
No Change  
No Change  
Latched  
X
1
1
operation, V and V  
should be constrained  
in out  
to the range V  
(V or V  
)
V
DD  
.
0
X
X
X
X
SS in out  
Unused inputs must always be tied to an  
appropriate logic voltage level (e.g., either V  
X
X
X
SS  
or V ). Unused outputs must be left open.  
1
0
Latched  
Q0 = Q1 = Q2 = Q3 = 0  
DD  
X = Don’t Care  
REV 3  
1/94  
Motorola, Inc. 1995  
12345678

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