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MC145532DW PDF预览

MC145532DW

更新时间: 2024-11-28 22:58:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 转换器PC
页数 文件大小 规格书
16页 223K
描述
ADPCM Transcoder

MC145532DW 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.86
其他特性:FULL DUPLEX压伸定律:A/MU-LAW
滤波器:NOJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:10.3 mm
功能数量:1端子数量:16
工作模式:SYNCHRONOUS/ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:2.65 mm
标称供电电压:5 V表面贴装:YES
电信集成电路类型:ADPCM CODEC温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm

MC145532DW 数据手册

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Order this document  
by MC145532/D  
SEMICONDUCTOR TECHNICAL DATA  
Conforms to G.721–1988 and T1.301–1987  
DW SUFFIX  
SOG PACKAGE  
CASE 751G  
16  
The MC145532 Adaptive Differential Pulse Code Modulation (ADPCM)  
Transcoder provides a low–cost, full–duplex, single–channel transcoder to  
(from) a 64 kbps PCM channel from (to) either a 16 kbps, 24 kbps, 32 kbps, or  
64 kbps channel.  
1
Complies with CCITT Recommendation G.721–1988  
Complies with the American National Standard (T1.301–1987)  
Full–Duplex, Single–Channel Operation  
Mu–Law or A–Law Coding is Pin Selectable  
Synchronous or Asynchronous Operation  
Easily Interfaces with Any Member of Motorola’s PCM Codec–Filter  
Mono–Circuit Family or Other Industry Standard Codec  
Serial PCM and ADPCM Data Transfer Rate from 64 kbps to 5.12 Mbps  
Power–Down Capability for Low Current Consumption  
The Reset State, an Option Specified in the Standards, is Automatically  
Initiated When the RESET Pin is Released  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620  
16  
1
ORDERING INFORMATION  
MC145532DW SOG Package  
MC145532L Ceramic Package  
PIN ASSIGNMENT  
Simple Time Slot Assignment Timing for Transcoder Applications  
Single 5 V Power Supply  
16–Pin Package  
The MC145536EVK is the Evaluation Platform for the MC145532 and Also  
Includes the MC145480 5 V PCM Codec–Filter  
MODE  
DDO  
DOE  
DDC  
DDI  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
DD  
EDO  
EOE  
EDC  
EDI  
DIE  
EIE  
RESET  
SPC  
APD  
V
SS  
BLOCK DIAGRAM  
DDO  
EDO  
EDE  
I/O DATA BUS  
DOE  
REG  
S REG  
S REG  
LATCH  
REG  
S REG  
S REG  
DDC  
DDI  
EDC  
EDI  
DIGITAL  
SIGNAL  
PROCESSOR  
LATCH  
DIE  
EIE  
RESET  
SPC  
MODE  
APD  
V
V
DD  
SS  
REV 1  
9/95 (Replaces NP470)  
Motorola, Inc. 1995  

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