MC14516B
Binary Up/Down Counter
The MC14516B synchronous up/down binary counter is
constructed with MOS P−channel and N−channel enhancement mode
devices in a monolithic structure.
This counter can be preset by applying the desired value, in binary,
to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset
Enable (PE) high. The direction of counting is controlled by applying
a high (for up counting) or a low (for down counting) to the
UP/DOWN input. The state of the counter changes on the positive
transition of the clock input.
http://onsemi.com
MARKING
DIAGRAMS
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high
to the reset (R) pin.
This CMOS counter finds primary use in up/down and difference
counting. Other applications include: (1) Frequency synthesizer
applications where low power dissipation and/or high noise immunity
is desired, (2) Analog−to−Digital and Digital−to−Analog conversions,
and (3) Magnitude and sign generation.
16
PDIP−16
P SUFFIX
CASE 648
MC14516BCP
AWLYYWWG
1
1
16
SOIC−16
D SUFFIX
CASE 751B
14516BG
AWLYWW
Features
1
1
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Internally Synchronous for High Speed
• Logic Edge−Clocked Design — Count Occurs on Positive Going
Edge of Clock
16
SOEIAJ−16
F SUFFIX
CASE 966
MC14516B
ALYWG
1
1
• Single Pin Reset
• Asynchronous Preset Enable Operation
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky Load Over the Rated Temperature Range
• Pb−Free Packages are Available*
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
ORDERING INFORMATION
Parameter
Symbol
Value
Unit
V
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
DC Supply Voltage Range
V
−0.5 to +18.0
DD
Input or Output Voltage Range
(DC or Transient)
V , V
−0.5 to V
+ 0.5
V
in out
DD
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated
voltages to this high−impedance circuit. For proper
operation, V and V should be constrained to the
Input or Output Current (DC or Transient) I , I
per Pin
10
mA
in out
Power Dissipation, per Package (Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature (8−Second Soldering)
P
T
500
mW
°C
D
−55 to +125
−65 to +150
260
A
in
out
range V v (V or V ) v V
.
DD
SS
in
out
T
stg
°C
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either V or V ). Unused
T
°C
L
SS
DD
outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 7
MC14516B/D