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MC14516BCPD PDF预览

MC14516BCPD

更新时间: 2024-11-03 13:11:15
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摩托罗拉 - MOTOROLA 计数器
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10页 261K
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MC14516BCPD 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC14516B synchronous up/down binary counter is constructed with  
MOS P–channel and N–channel enhancement mode devices in a monolithic  
structure.  
L SUFFIX  
CERAMIC  
CASE 620  
This counter can be preset by applying the desired value, in binary, to the  
Preset inputs (P0, P1, P2, P3) and then bringing the Preset Enable (PE)  
high. The direction of counting is controlled by applying a high (for up  
counting) or a low (for down counting) to the UP/DOWN input. The state of  
the counter changes on the positive transition of the clock input.  
Cascading can be accomplished by connecting the Carry Out to the  
Carry In of the next stage while clocking each counter in parallel. The  
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high to the  
reset (R) pin.  
P SUFFIX  
PLASTIC  
CASE 648  
D SUFFIX  
SOIC  
This CMOS counter finds primary use in up/down and difference counting.  
Other applications include: (1) Frequency synthesizer applications where  
low power dissipation and/or high noise immunity is desired, (2) Analog–to–  
digital and digital–to–analog conversions, and (3) Magnitude and sign  
generation.  
CASE 751B  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
Diode Protection on All Inputs  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Internally Synchronous for High Speed  
T
A
= – 55° to 125°C for all packages.  
Logic Edge–Clocked Design — Count Occurs on Positive Going Edge  
of Clock  
Single Pin Reset  
BLOCK DIAGRAM  
Asynchronous Preset Enable Operation  
Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky Load Over the Rated Temperature Range  
PE  
1
6
Q0  
Q1  
Q2  
Q3  
CARRY IN  
RESET  
UP/DOWN  
CLOCK  
P0  
5
9
11  
14  
2
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
10  
15  
4
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
V
– 0.5 to + 18.0  
DD  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
I , I  
P1  
12  
13  
3
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
in out  
P2  
CARRY  
OUT  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
P3  
7
T
stg  
– 65 to + 150  
260  
T
L
Lead Temperature (8–Second Soldering)  
C
V
V
= PIN 16  
= PIN 8  
DD  
SS  
* Maximum Ratings are those values beyond which damage to the device may occur.  
Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
This device contains protection circuitry to  
guard against damage due to high static  
voltages or electric fields. However, pre-  
cautions must be taken to avoid applications of  
any voltage higher than maximum rated volt-  
ages to this high–impedance circuit. For proper  
TRUTH TABLE  
Preset  
Enable  
Carry In  
Up/Down  
Reset  
Clock  
Action  
No Count  
Count Up  
Count Down  
Preset  
1
X
1
0
0
0
1
X
0
0
0
0
1
X
operation, V and V  
should be constrained  
in  
out  
0
to the range V  
(V or V  
in out  
)
V
DD  
.
SS  
0
0
Unused inputs must always be tied to an  
appropriatelogic voltage level (e.g., either V  
X
X
X
X
X
SS  
or V ). Unused outputs must be left open.  
DD  
X
Reset  
X = Don’t Care  
NOTE: When counting up, the Carry Out signal is normally high and is low only  
when Q0 through Q3 are high and Carry In is low. When counting down,  
Carry Out is low only when Q0 through Q3 and Carry In are low.  
REV 3  
1/94  
Motorola, Inc. 1995  

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