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MC14516BCPDS

更新时间： 2024-02-14 07:53:54
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器
页数 文件大小 规格书
10页 261K
描述
Binary Counter, 4000/14000/40000 Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, PDIP16, CERAMIC, DIP-16

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MC14516BCPDS 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：LEAD FREE, EIAJ, SOP-16
针数：16Reach Compliance Code：unknown
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.64Is Samacsys：N
计数方向：BIDIRECTIONAL系列：4000/14000/40000
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：10.2 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：1500000 Hz工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：5/15 V
传播延迟（tpd）：630 ns认证状态：Not Qualified
座面最大高度：2.05 mm子类别：Counters
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40触发器类型：POSITIVE EDGE
宽度：5.275 mm最小 fmax：4 MHz
Base Number Matches：1

MC14516BCPDS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC14516B synchronous up/down binary counter is constructed with  
MOS P–channel and N–channel enhancement mode devices in a monolithic  
structure.  
L SUFFIX  
CERAMIC  
CASE 620  
This counter can be preset by applying the desired value, in binary, to the  
Preset inputs (P0, P1, P2, P3) and then bringing the Preset Enable (PE)  
high. The direction of counting is controlled by applying a high (for up  
counting) or a low (for down counting) to the UP/DOWN input. The state of  
the counter changes on the positive transition of the clock input.  
Cascading can be accomplished by connecting the Carry Out to the  
Carry In of the next stage while clocking each counter in parallel. The  
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high to the  
reset (R) pin.  
P SUFFIX  
PLASTIC  
CASE 648  
D SUFFIX  
SOIC  
This CMOS counter finds primary use in up/down and difference counting.  
Other applications include: (1) Frequency synthesizer applications where  
low power dissipation and/or high noise immunity is desired, (2) Analog–to–  
digital and digital–to–analog conversions, and (3) Magnitude and sign  
generation.  
CASE 751B  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
•
•
•
•
Diode Protection on All Inputs  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Internally Synchronous for High Speed  
T
A
= – 55° to 125°C for all packages.  
Logic Edge–Clocked Design — Count Occurs on Positive Going Edge  
of Clock  
Single Pin Reset  
BLOCK DIAGRAM  
•
•
•
Asynchronous Preset Enable Operation  
Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky Load Over the Rated Temperature Range  
PE  
1
6
Q0  
Q1  
Q2  
Q3  
CARRY IN  
RESET  
UP/DOWN  
CLOCK  
P0  
5
9
11  
14  
2
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
10  
15  
4
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
V
– 0.5 to + 18.0  
DD  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
I , I  
P1  
12  
13  
3
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
in out  
P2  
CARRY  
OUT  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
P3  
7
T
stg  
– 65 to + 150  
260  
T
L
Lead Temperature (8–Second Soldering)  
C
V
V
= PIN 16  
= PIN 8  
DD  
SS  
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
This device contains protection circuitry to  
guard against damage due to high static  
voltages or electric fields. However, pre-  
cautions must be taken to avoid applications of  
any voltage higher than maximum rated volt-  
ages to this high–impedance circuit. For proper  
TRUTH TABLE  
Preset  
Enable  
Carry In  
Up/Down  
Reset  
Clock  
Action  
No Count  
Count Up  
Count Down  
Preset  
1
X
1
0
0
0
1
X
0
0
0
0
1
X
operation, V and V  
should be constrained  
in  
out  
0
to the range V  
(V or V  
in out  
)
V
DD  
.
SS  
0
0
Unused inputs must always be tied to an  
appropriatelogic voltage level (e.g., either V  
X
X
X
X
X
SS  
or V ). Unused outputs must be left open.  
DD  
X
Reset  
X = Don’t Care  
NOTE: When counting up, the Carry Out signal is normally high and is low only  
when Q0 through Q3 are high and Carry In is low. When counting down,  
Carry Out is low only when Q0 through Q3 and Carry In are low.  
REV 3  
1/94  
Motorola, Inc. 1995  
1234567...10

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