The MC14076B 4–Bit Register consists of four D–type flip–flops
operating synchronously from a common clock. OR gated
output–disable inputs force the outputs into a high–impedance state
for use in bus organized systems. OR gated data–disable inputs cause
the Q outputs to be fed back to the D inputs of the flip–flops. Thus they
are inhibited from changing state while the clocking process remains
undisturbed. An asynchronous master root is provided to clear all four
flip–flops simultaneously independent of the clock or disable inputs.
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
• Three–State Outputs with Gated Control Lines
• Fully Independent Clock Allows Unrestricted Operation for the Two
Modes: Parallel Load and Do Nothing
MC14076BCP
AWLYYWW
1
• Asynchronous Master Reset
• Four Bus Buffer Registers
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
16
SOIC–16
D SUFFIX
CASE 751B
14076B
AWLYWW
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
1
Schottky TTL Load Over the Rated Temperature Range
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 1.)
SS
Symbol
Parameter
Value
Unit
V
V
DD
DC Supply Voltage Range
–0.5 to +18.0
ORDERING INFORMATION
V , V
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
in out
DD
Device
Package
PDIP–16
SOIC–16
Shipping
MC14076BCP
MC14076BD
2000/Box
2400/Box
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
P
D
Power Dissipation,
per Package (Note 2.)
500
mW
MC14076BDR2
SOIC–16 2500/Tape & Reel
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
T
stg
T
Lead Temperature
L
(8–Second Soldering)
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14076B/D