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MC14077BCPD

更新时间： 2024-11-04 13:11:15
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摩托罗拉 - MOTOROLA 栅
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MC14077BCPD 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
Quad Exclusive “OR” and “NOR” Gates  
The MC14070B quad exclusive OR gate and the MC14077B quad  
exclusive NOR gate are constructed with MOS P–channel and N–channel  
enhancement mode devices in a single monolithic structure. These  
complementary MOS logic gates find primary use where low power  
dissipation and/or high noise immunity is desired.  
L SUFFIX  
CERAMIC  
CASE 632  
•
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
All Outputs Buffered  
P SUFFIX  
PLASTIC  
CASE 646  
Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky TTL Load Over the Rated Temperature Range  
Double Diode Protection on All Inputs  
MC14070B — Replacement for CD4030B and CD4070B Types  
MC14077B — Replacement for CD4077B Type  
•
•
•
D SUFFIX  
SOIC  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
CASE 751A  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
V
DD  
– 0.5 to + 18.0  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
V , V  
in out  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
I , I  
in out  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
T
A
= – 55° to 125°C for all packages.  
P
D
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
T
stg  
– 65 to + 150  
260  
MC14070B  
QUAD Exclusive OR QUAD Exclusive NOR  
Gate Gate  
MC14077B  
T
L
Lead Temperature (8–Second Soldering)  
C
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
1
1
3
4
3
2
5
2
5
20 ns  
20 ns  
4
V
V
V
DD  
6
8
DD  
6
8
90%  
50%  
10%  
10  
11  
10  
11  
V
in  
I
SS  
DD  
9
12  
9
12  
1/f  
50% DUTY CYCLE  
V
in  
*
13  
13  
C
L
V
V
= PIN 14  
= PIN 7  
(BOTH DEVICES)  
DD  
SS  
* Inverted output on MC14077B only.  
Figure 1. Power Dissipation Test Circuit and Waveform  
20 ns  
20 ns  
V
DD  
PIN ASSIGNMENT  
V
DD  
90%  
50%  
10%  
PULSE  
GENERATOR  
IN 1  
IN 2  
1
2
3
4
14  
13  
12  
11  
V
DD  
A
INPUT  
*
V
V
IN 2  
#
SS  
A
D
D
t
t
PHL  
PLH  
C
L
OUT  
IN 1  
A
OH  
90%  
50%  
10%  
V
SS  
OUTPUT  
t
OUT  
OUT  
OUT  
B
D
C
V
OL  
IN 1  
5
6
10  
9
t
B
B
THL  
TLH  
* Inverted output on MC14077B only.  
#Connect unused input to V for MC14070B, to V  
IN 2  
IN 2  
C
for MC14077B.  
DD SS  
V
7
8
IN 1  
SS  
C
Figure 2. Switching Time Test Circuit and Waveforms  
REV 3  
1/94  
Motorola, Inc. 1995  
1234

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