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MC14077BDG PDF预览

MC14077BDG

更新时间: 2024-11-20 04:59:31
品牌 Logo 应用领域
安森美 - ONSEMI
页数 文件大小 规格书
7页 134K
描述
CMOS SSI Quad Exclusive OR and NOR Gates

MC14077BDG 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:0.8
Samacsys Description:NULL系列:4000/14000/40000
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:XNOR GATE湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:RAIL峰值回流温度(摄氏度):260
电源:5/15 VProp。Delay @ Nom-Sup:350 ns
传播延迟(tpd):350 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):18 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3.9 mm

MC14077BDG 数据手册

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MC14070B, MC14077B  
CMOS SSI  
Quad Exclusive “OR” and “NOR” Gates  
The MC14070B quad exclusive OR gate and the MC14077B quad  
exclusive NOR gate are constructed with MOS Pchannel and  
Nchannel enhancement mode devices in a single monolithic  
structure. These complementary MOS logic gates find primary use  
where low power dissipation and/or high noise immunity is desired.  
http://onsemi.com  
MARKING  
DIAGRAMS  
Features  
14  
1
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
All Outputs Buffered  
Capable of Driving Two LowPower TTL Loads or One LowPower  
Schottky TTL Load Over the Rated Temperature Range  
Double Diode Protection on All Inputs  
PDIP14  
P SUFFIX  
CASE 646  
MC140xxBCP  
AWLYYWWG  
MC14070B Replacement for CD4030B and CD4070B Types  
MC14077B Replacement for CD4077B Type  
PbFree Packages are Available  
14  
SOIC14  
D SUFFIX  
CASE 751A  
140xxBG  
AWLYWW  
1
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
0.5 to +18.0  
Unit  
V
14  
V
DC Supply Voltage Range  
SOEIAJ14  
F SUFFIX  
CASE 965  
DD  
MC140xxB  
ALYWG  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
0.5 to V + 0.5  
V
DD  
1
I , I  
Input or Output Current  
(DC or Transient) per Pin  
±10  
mA  
in out  
xx  
A
WL, L  
YY, Y  
= Specific Device Code  
= Assembly Location  
= Wafer Lot  
P
Power Dissipation, per Package  
(Note 1)  
500  
mW  
D
= Year  
T
A
Ambient Temperature Range  
Storage Temperature Range  
55 to +125  
65 to +150  
260  
°C  
°C  
°C  
WW, W = Work Week  
= PbFree Package  
G
T
stg  
T
Lead Temperature  
L
(8Second Soldering)  
ORDERING INFORMATION  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Temperature Derating:  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
highimpedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
October, 2006 Rev. 7  
MC14070B/D  
 

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