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MC14076BCLS

更新时间： 2024-11-16 13:11:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路输出元件
页数 文件大小 规格书
6页 238K
描述
D Flip-Flop, 4-Func, Positive Edge Triggered, CMOS, CDIP16

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中文翻译

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MC14076BCLS 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：unknown
风险等级：5.92JESD-30 代码：R-XDIP-T16
JESD-609代码：e0逻辑集成电路类型：D FLIP-FLOP
功能数量：4端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：CERAMIC
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
电源：5/15 V认证状态：Not Qualified
子类别：FF/Latches表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
触发器类型：POSITIVE EDGEBase Number Matches：1

MC14076BCLS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 620  
The MC14076B 4–Bit Register consists of four D–type flip–flops operating  
synchronously from a common clock. OR gated output–disable inputs force  
the outputs into a high–impedance state for use in bus organized systems.  
OR gated data–disable inputs cause the Q outputs to be fed back to the D  
inputs of the flip–flops. Thus they are inhibited from changing state while the  
clocking process remains undisturbed. An asynchronous master root is  
provided to clear all four flip–flops simultaneously independent of the clock  
or disable inputs.  
P SUFFIX  
PLASTIC  
CASE 648  
D SUFFIX  
SOIC  
CASE 751B  
•
•
Three–State Outputs with Gated Control Lines  
Fully Independent Clock Allows Unrestricted Operation for the Two  
Modes: Parallel Load and Do Nothing  
•
•
•
•
Asynchronous Master Reset  
Four Bus Buffer Registers  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky TTL Load Over the Rated Temperature Range  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
T
= – 55° to 125°C for all packages.  
A
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
BLOCK DIAGRAM  
V
DD  
– 0.5 to + 18.0  
RESET  
D0  
Q0  
Q1  
Q2  
Q3  
15  
3
4
5
6
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
14  
13  
12  
11  
10  
9
I , I  
in out  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
D1  
D2  
P
D
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D3  
DATA  
DISABLE  
T
stg  
– 65 to + 150  
260  
B
A
T
L
Lead Temperature (8–Second Soldering)  
C
7
CLOCK  
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
2
B
A
OUTPUT  
DISABLE  
1
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
V
V
= PIN 16  
= PIN 8  
DD  
SS  
FUNCTION TABLE  
Inputs  
Data Disable  
Data  
D
Output  
Q
Reset  
Clock  
A
B
1
0
0
0
0
0
X
0
X
X
1
X
0
0
X
X
X
1
0
0
X
X
X
X
0
0
Q
Q
Q
n
n
n
0
1
1
When either output disable A or B (or both) is (are) high the  
output is disabled to the high–impedance state; however  
sequential operation of the flip–flops is not affected.  
X = Don’t Care.  
REV 3  
1/94  
Motorola, Inc. 1995  
123456

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