MC14070B, MC14077B
CMOS SSI
Quad Exclusive “OR” and “NOR” Gates
The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS P−channel and
N−channel enhancement mode devices in a single monolithic
structure. These complementary MOS logic gates find primary use
where low power dissipation and/or high noise immunity is desired.
http://onsemi.com
MARKING
DIAGRAMS
Features
14
1
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Double Diode Protection on All Inputs
• MC14070B − Replacement for CD4030B and CD4070B Types
• MC14077B − Replacement for CD4077B Type
• These Devices are Pb−Free and are RoHS Compliant
PDIP−14
P SUFFIX
CASE 646
MC140xxBCP
AWLYYWWG
14
SOIC−14
D SUFFIX
CASE 751A
140xxBG
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
Symbol
Parameter
Value
−0.5 to +18.0
Unit
V
14
V
DD
DC Supply Voltage Range
SOEIAJ−14
F SUFFIX
CASE 965
MC140xxB
ALYWG
V , V
in out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V + 0.5
V
DD
1
I , I
Input or Output Current
(DC or Transient) per Pin
10
mA
in out
xx
A
WL, L
YY, Y
= Specific Device Code
= Assembly Location
= Wafer Lot
P
D
Power Dissipation, per Package
(Note 1)
500
mW
= Year
T
A
Ambient Temperature Range
Storage Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
WW, W = Work Week
= Pb−Free Package
G
T
stg
T
L
Lead Temperature
(8−Second Soldering)
ORDERING INFORMATION
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
June, 2011 − Rev. 8
MC14070B/D