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MC14042BFL2 PDF预览

MC14042BFL2

更新时间： 2024-02-04 04:54:56
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路
页数 文件大小 规格书
8页 174K
描述
IC,LATCH,QUAD,1-BIT,CMOS,SOP,16PIN,PLASTIC

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中文翻译

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MC14042BFL2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：SOP, SOP16,.3Reach Compliance Code：not_compliant
风险等级：5.87JESD-30 代码：R-PDSO-G16
JESD-609代码：e0负载电容（CL）：50 pF
逻辑集成电路类型：D LATCH位数：1
功能数量：4端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TAPE AND REEL
电源：5/15 VProp。Delay @ Nom-Sup：440 ns
认证状态：Not Qualified子类别：FF/Latches
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUALBase Number Matches：1

MC14042BFL2 数据手册

 浏览型号MC14042BFL2的Datasheet PDF文件第2页浏览型号MC14042BFL2的Datasheet PDF文件第3页浏览型号MC14042BFL2的Datasheet PDF文件第4页浏览型号MC14042BFL2的Datasheet PDF文件第5页浏览型号MC14042BFL2的Datasheet PDF文件第6页浏览型号MC14042BFL2的Datasheet PDF文件第7页 
The MC14042B Quad Transparent Latch is constructed with MOS  
P–channel and N–channel enhancement mode devices in a single  
monolithic structure. Each latch has a separate data input, but all four  
latches share a common clock. The clock polarity (high or low) used to  
strobe data through the latches can be reversed using the polarity  
input. Information present at the data input is transferred to outputs Q  
and Q during the clock level which is determined by the polarity input.  
When the polarity input is in the logic “0” state, data is transferred  
during the low clock level, and when the polarity input is in the logic  
“1” state the transfer occurs during the high clock level.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP–16  
P SUFFIX  
CASE 648  
MC14042BCP  
AWLYYWW  
• Buffered Data Inputs  
• Common Clock  
• Clock Polarity Control  
• Q and Q Outputs  
1
16  
• Double Diode Input Protection  
• Supply Voltage Range = 3.0 Vdc to 1 8 Vdc  
SOIC–16  
D SUFFIX  
CASE 751B  
14042B  
AWLYWW  
• Capable of Driving Two Low–power TTL Loads or One Low–power  
1
Schottky TTL Load Over the Rated Temperature Range  
16  
SOEIAJ–16  
F SUFFIX  
CASE 966  
MC14042B  
AWLYWW  
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)  
SS  
Symbol  
Parameter  
Value  
Unit  
V
1
V
DD  
DC Supply Voltage Range  
–0.5 to +18.0  
A
= Assembly Location  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
–0.5 to V + 0.5  
V
DD  
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
±10  
mA  
P
D
Power Dissipation,  
per Package (Note 3.)  
500  
mW  
ORDERING INFORMATION  
T
Ambient Temperature Range  
Storage Temperature Range  
–55 to +125  
–65 to +150  
260  
°C  
°C  
°C  
Device  
Package  
PDIP–16  
SOIC–16  
Shipping  
A
T
stg  
MC14042BCP  
MC14042BD  
2000/Box  
2400/Box  
T
Lead Temperature  
(8–Second Soldering)  
L
MC14042BDR2  
SOIC–16 2500/Tape & Reel  
2. Maximum Ratings are those values beyond which damage to the device  
may occur.  
3. Temperature Derating:  
MC14042BF  
SOEIAJ–16  
SOEIAJ–16  
SOEIAJ–16  
SOEIAJ–16  
See Note 1.  
See Note 1.  
See Note 1.  
See Note 1.  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
MC14042BFEL  
MC14042BFR1  
MC14042BFR2  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high–impedancecircuit. For proper operation, V and V should be constrained  
in  
out  
to the range V  
(V or V  
)
V
.
1. For ordering information on the EIAJ version of  
the SOIC packages, please contact your local  
ON Semiconductor representative.  
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
either V or V ). Unused outputs must be left open.  
SS  
DD  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 3  
MC14042B/D  
12345678

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