Datasheet > MC14042B_05

MC14042B_05

更新时间： 2024-11-12 04:59:31

品牌	Logo	应用领域
安森美 - ONSEMI		锁存器
页数	文件大小	规格书
8页	101K
描述
Quad Transparent Latch

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中文翻译

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MC14042B_05 数据手册

MC14042B

Quad Transparent Latch

The MC14042B Quad Transparent Latch is constructed with MOS

P−channel and N−channel enhancement mode devices in a single

monolithic structure. Each latch has a separate data input, but all four

latches share a common clock. The clock polarity (high or low) used to

strobe data through the latches can be reversed using the polarity

input. Information present at the data input is transferred to outputs Q

and Q during the clock level which is determined by the polarity input.

When the polarity input is in the logic “0” state, data is transferred

during the low clock level, and when the polarity input is in the logic

“1” state the transfer occurs during the high clock level.

http://onsemi.com

MARKING

DIAGRAMS

PDIP−16

P SUFFIX

CASE 648

MC14042BCP

AWLYYWWG

Features

• Buffered Data Inputs

• Common Clock

• Clock Polarity Control

• Q and Q Outputs

SOIC−16

D SUFFIX

CASE 751B

14042BG

AWLYWW

• Double Diode Input Protection

• Supply Voltage Range = 3.0 Vdc to 1 8 Vdc

• Capable of Driving Two Low−power TTL Loads or One Low−power

Schottky TTL Load Over the Rated Temperature Range

• Pb−Free Packages are Available*

SOEIAJ−16

F SUFFIX

CASE 966

MC14042B

ALYWG

MAXIMUM RATINGS (Voltages Referenced to V

)

Symbol

Parameter

Value

Unit

DC Supply Voltage Range

−0.5 to +18.0

V , V

Input or Output Voltage Range

(DC or Transient)

−0.5 to V + 0.5

WL, L

YY, Y

= Assembly Location

= Wafer Lot

= Year

in out

I , I

in out

Input or Output Current

(DC or Transient) per Pin

WW, W = Work Week

= Pb−Free Indicator

Power Dissipation,

per Package (Note 1)

500

Ambient Temperature Range

Storage Temperature Range

−55 to +125

−65 to +150

260

°C

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

stg

Lead Temperature

(8−Second Soldering)

Maximum ratings are those values beyond which device damage can occur.

Maximum ratings applied to the device are individual stress limit values (not

normal operating conditions) and are not valid simultaneously. If these limits are

exceeded, device functional operation is not implied, damage may occur and

reliability may be affected.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, V and V should be constrained

out

to the range V v (V or V ) v V

out

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either V or V ). Unused outputs must be left open.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2005

Publication Order Number:

August, 2005 − Rev. 6

MC14042B/D

12 3 4 5 6 7 8

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与MC14042B_05相关器件

型号	品牌	获取价格	描述	数据表
MC14042BAL	MOTOROLA	获取价格	D Latch, 4000/14000/40000 Series, 1-Func, High Level Triggered, 4-Bit, Complementary Outpu
MC14042BALD	MOTOROLA	获取价格	4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CDIP16, 620-0
MC14042BALDS	MOTOROLA	获取价格	暂无描述
MC14042BALS	MOTOROLA	获取价格	IC,LATCH,QUAD,1-BIT,CMOS,DIP,16PIN,CERAMIC
MC14042BCL	MOTOROLA	获取价格	QUAD TRANSPARENT LATCH
MC14042BCLD	MOTOROLA	获取价格	D Latch, 4000/14000/40000 Series, 1-Func, High Level Triggered, 4-Bit, Complementary Outpu
MC14042BCLDS	MOTOROLA	获取价格	4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CDIP16, 620-0
MC14042BCLS	MOTOROLA	获取价格	D Latch, 4-Func, 1-Bit, CMOS, CDIP16
MC14042BCP	MOTOROLA	获取价格	QUAD TRANSPARENT LATCH
MC14042BCP	ONSEMI	获取价格	Quad Transparent Latch

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