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MC14042BCL PDF预览

MC14042BCL

更新时间: 2024-11-12 04:59:31
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路
页数 文件大小 规格书
6页 203K
描述
QUAD TRANSPARENT LATCH

MC14042BCL 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP,
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.37
Is Samacsys:N其他特性:PROGRAMMABLE TRIGGER TYPE
系列:4000/14000/40000JESD-30 代码:R-GDIP-T16
JESD-609代码:e0长度:19.495 mm
负载电容(CL):50 pF逻辑集成电路类型:D LATCH
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):440 ns
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):18 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:HIGH LEVEL
宽度:7.62 mmBase Number Matches:1

MC14042BCL 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 620  
The MC14042B Quad Transparent Latch is constructed with MOS  
P–channel and N–channel enhancement mode devices in a single  
monolithic structure. Each latch has a separate data input, but all four  
latches share a common clock. The clock polarity (high or low) used to  
strobe data through the latches can be reversed using the polarity input.  
Information present at the data input is transferred to outputs Q and Q during  
the clock level which is determined by the polarity input. When the polarity  
input is in the logic “0” state, data is transferred during the low clock level,  
and when the polarity input is in the logic “1” state the transfer occurs during  
the high clock level.  
P SUFFIX  
PLASTIC  
CASE 648  
D SUFFIX  
SOIC  
CASE 751B  
Buffered Data Inputs  
Common Clock  
Clock Polarity Control  
Q and Q Outputs  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
Double Diode Input Protection  
Supply Voltage Range = 3.0 Vdc to 1 8 Vdc  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range  
T
A
= – 55° to 125°C for all packages.  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
PIN ASSIGNMENT  
V
DD  
– 0.5 to + 18.0  
Q3  
Q0  
1
2
16  
15  
V
DD  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
l , l  
Q3  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
in out  
Q0  
D0  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
D3  
D2  
Q2  
Q2  
Q1  
Q1  
P
D
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
CLOCK  
T
stg  
– 65 to + 150  
260  
T
L
Lead Temperature (8–Second Soldering)  
C
POLARITY  
D1  
* Maximum Ratings are those values beyond which damage to the device may occur.  
Temperature Derating:  
V
SS  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
LOGIC DIAGRAM  
TRUTH TABLE  
Polarity  
D0  
D1  
D2  
D3  
Q0  
Q0  
LATCH  
1
5
6
4
7
2
3
Clock  
Q
CLOCK  
POLARITY  
0
1
1
0
0
0
1
1
Data  
Latch  
Data  
Latch  
Q1  
Q1  
LATCH  
2
10  
9
Q2  
Q2  
LATCH  
3
13  
14  
11  
12  
V
V
= PIN 16  
= PIN 8  
DD  
SS  
Q3  
Q3  
LATCH  
4
1
REV 3  
1/94  
Motorola, Inc. 1995  

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