MC14027

更新时间： 2024-11-03 22:58:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器
页数	文件大小	规格书
6页	217K
描述
Dual J-K Flip-Flop

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中文翻译

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数据手册

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MC14027 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC14027B dual J–K flip–flop has independent J, K, Clock (C), Set (S)

and Reset (R) inputs for each flip–flop. These devices may be used in

control, register, or toggle functions.

L SUFFIX

CERAMIC

CASE 620

•

Diode Protection on All Inputs

Supply Voltage Range = 3.0 Vdc to 18 Vdc

Logic Swing Independent of Fanout

P SUFFIX

PLASTIC

CASE 648

Logic Edge–Clocked Flip–Flop Design —

Logic state is retained indefinitely with clock level either high or low;

information is transferred to the output only on the positive–going edge

of the clock pulse

•

Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

Pin–for–Pin Replacement for CD4027B

D SUFFIX

SOIC

CASE 751B

MAXIMUM RATINGS* (Voltages Referenced to V

)

ORDERING INFORMATION

Symbol

Parameter

DC Supply Voltage

Value

Unit

MC14XXXBCP

MC14XXXBCL

MC14XXXBD

Plastic

Ceramic

SOIC

– 0.5 to + 18.0

V , V

Input or Output Voltage (DC or Transient)

– 0.5 to V

+ 0.5

in out

l , l

= – 55° to 125°C for all packages.

Input or Output Current (DC or Transient),

per Pin

± 10

in out

Power Dissipation, per Package†

Storage Temperature

500

BLOCK DIAGRAM

stg

– 65 to + 150

260

Lead Temperature (8–Second Soldering)

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C

TRUTH TABLE

Inputs

Outputs*

†

‡

n+1

Change

= PIN 16

= PIN 8

‡

X = Don’t Care

= Level Change

= Present State

* = Next State

†

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must

be taken to avoid applications of any voltage higher than maximum rated

voltages to this high-impedance circuit. For proper operation, V and

out

should be constrained to the range V

≤ (V or V ) ≤ V .

in out DD

Unused inputs must always be tied to an appropriate logic voltage

level (e.g., either V or V ). Unused outputs must be left open.

SS DD

REV 3

1/94

Motorola, Inc. 1995

MOTOROLA CMOS LOGIC DATA

MC14027B

107

12 3 4 5 6

中文翻译

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与MC14027相关器件

型号	品牌	获取价格	描述	数据表
MC14027B	ONSEMI	获取价格	Dual J-K Flip-Flop
MC14027B	MOTOROLA	获取价格	Dual J-K Flip-Flop
MC14027B_05	ONSEMI	获取价格	Dual J−K Flip−Flop
MC14027BAL	MOTOROLA	获取价格	4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT,
MC14027BALD	MOTOROLA	获取价格	4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT,
MC14027BALDS	MOTOROLA	获取价格	J-K Flip-Flop, 4000/14000/40000 Series, 2-Func, Positive Edge Triggered, 2-Bit, Complement
MC14027BBEBS	MOTOROLA	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,CMOS,DIP,16PIN,CERAMIC
MC14027BCL	MOTOROLA	获取价格	4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT,
MC14027BCLD	MOTOROLA	获取价格	4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT,
MC14027BCLS	MOTOROLA	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,CMOS,DIP,16PIN,CERAMIC

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