MC14027BD

更新时间： 2024-11-19 22:58:11

品牌	Logo	应用领域
安森美 - ONSEMI		触发器
页数	文件大小	规格书
8页	187K
描述
Dual J-K Flip-Flop

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中文翻译

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数据手册
替代型号

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MC14027BD 数据手册

The MC14027B dual J–K flip–flop has independent J, K, Clock (C),

Set (S) and Reset (R) inputs for each flip–flop. These devices may be

used in control, register, or toggle functions.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Logic Swing Independent of Fanout

http://onsemi.com

• Logic Edge–Clocked Flip–Flop Design —

MARKING

DIAGRAMS

Logic state is retained indefinitely with clock level either high or low;

information is transferred to the output only on the positive–going

edge of the clock pulse

PDIP–16

P SUFFIX

CASE 648

MC14027BCP

AWLYYWW

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• Pin–for–Pin Replacement for CD4027B

SOIC–16

D SUFFIX

CASE 751B

14027B

AWLYWW

MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)

Symbol

Parameter

Value

Unit

DC Supply Voltage Range

–0.5 to +18.0

V , V

Input or Output Voltage Range

(DC or Transient)

–0.5 to V + 0.5

in out

SOEIAJ–16

F SUFFIX

CASE 966

MC14027B

AWLYWW

I , I

in out

Input or Output Current

(DC or Transient) per Pin

±10

Power Dissipation,

500

per Package (Note 3.)

= Assembly Location

Ambient Temperature Range

Storage Temperature Range

–55 to +125

–65 to +150

260

°C

WL or L = Wafer Lot

YY or Y = Year

WW or W = Work Week

stg

Lead Temperature

(8–Second Soldering)

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

ORDERING INFORMATION

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

Device

Package

PDIP–16

SOIC–16

Shipping

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

MC14027BCP

MC14027BD

2000/Box

2400/Box

high–impedancecircuit. For proper operation, V and V should be constrained

out

MC14027BDR2

SOIC–16 2500/Tape & Reel

to the range V

(V or V

)

out

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either V or V ). Unused outputs must be left open.

MC14027BF

SOEIAJ–16

See Note 1.

MC14027BFEL

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local

ON Semiconductor representative.

Semiconductor Components Industries, LLC, 2000

Publication Order Number:

March, 2000 – Rev. 3

MC14027B/D

12 3 4 5 6 7 8

中文翻译

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MC14027BD 替代型号

型号	品牌	替代类型	描述	数据表
MC14027BCP	ONSEMI	完全替代	Dual J-K Flip-Flop
MC14027BDR2G	ONSEMI	类似代替	Dual J−K Flip−Flop
MC14027BDG	ONSEMI	类似代替	Dual J−K Flip−Flop

与MC14027BD相关器件

型号	品牌	获取价格	描述	数据表
MC14027BDEBS	MOTOROLA	获取价格	J-K Flip-Flop, 2-Func, Master-slave Triggered, CMOS, CDIP16
MC14027BDG	ONSEMI	获取价格	Dual J−K Flip−Flop
MC14027BDR2	MOTOROLA	获取价格	4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT,
MC14027BDR2	ONSEMI	获取价格	Dual J-K Flip-Flop
MC14027BDR2G	ONSEMI	获取价格	Dual J−K Flip−Flop
MC14027BF	ONSEMI	获取价格	Dual J-K Flip-Flop
MC14027BFEL	ONSEMI	获取价格	Dual J-K Flip-Flop
MC14027BFELG	ONSEMI	获取价格	Dual J−K Flip−Flop
MC14027BFL2	ONSEMI	获取价格	4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT,
MC14027BFR1	ONSEMI	获取价格	4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT,

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