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MC14017BDR2G PDF预览

MC14017BDR2G

更新时间: 2024-11-16 12:36:35
品牌 Logo 应用领域
安森美 - ONSEMI 计数器触发器逻辑集成电路光电二极管PC
页数 文件大小 规格书
8页 144K
描述
Decade Counter

MC14017BDR2G 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:1.17
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:225135Samacsys Pin Count:16
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:SOIC-16 CASE751B-05Samacsys Released Date:2015-08-07 09:35:53
Is Samacsys:N计数方向:UP
系列:4000/14000/40000JESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:9.9 mm
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:RING COUNTER最大频率@ Nom-Sup:2000000 Hz
工作模式:SYNCHRONOUS湿度敏感等级:1
位数:10功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5/15 V传播延迟(tpd):1000 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Counters最大供电电压 (Vsup):18 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:6.7 MHzBase Number Matches:1

MC14017BDR2G 数据手册

 浏览型号MC14017BDR2G的Datasheet PDF文件第2页浏览型号MC14017BDR2G的Datasheet PDF文件第3页浏览型号MC14017BDR2G的Datasheet PDF文件第4页浏览型号MC14017BDR2G的Datasheet PDF文件第5页浏览型号MC14017BDR2G的Datasheet PDF文件第6页浏览型号MC14017BDR2G的Datasheet PDF文件第7页 
MC14017B  
Decade Counter  
The MC14017B is a fivestage Johnson decade counter with  
builtin code converter. High speed operation and spikefree outputs  
are obtained by use of a Johnson decade counter design. The ten  
decoded outputs are normally low, and go high only at their  
appropriate decimal time period. The output changes occur on the  
positivegoing edge of the clock pulse. This part can be used in  
frequency division applications as well as decade counter or decimal  
decode display applications.  
http://onsemi.com  
MARKING  
DIAGRAMS  
Features  
16  
1
Fully Static Operation  
PDIP16  
P SUFFIX  
CASE 648  
MC14017BCP  
AWLYYWWG  
DC Clock Input Circuit Allows Slow Rise Times  
Carry Out Output for Cascading  
DividebyN Counting  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
16  
Capable of Driving Two LowPower TTL Loads or One LowPower  
Schottky TTL Load Over the Rated Temperature Range  
PinforPin Replacement for CD4017B  
SOIC16  
D SUFFIX  
CASE 751B  
14017BG  
AWLYWW  
1
Triple Diode Protection on All Inputs  
These Devices are PbFree and are RoHS Compliant  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AECQ100  
Qualified and PPAP Capable  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
WW, W = Work Week  
G
= PbFree Indicator  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
0.5 to +18.0  
Unit  
V
V
DD  
DC Supply Voltage Range  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
0.5 to V + 0.5  
V
DD  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
P
D
Power Dissipation, per Package  
(Note 1)  
500  
mW  
T
Ambient Temperature Range  
Storage Temperature Range  
55 to +125  
65 to +150  
260  
°C  
°C  
°C  
A
T
stg  
T
Lead Temperature  
L
(8Second Soldering)  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
highimpedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
April, 2013 Rev. 8  
MC14017B/D  
 

MC14017BDR2G 替代型号

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