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MC14018BCLS

更新时间： 2024-11-16 13:11:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器
页数 文件大小 规格书
6页 215K
描述
Decade Counter, Synchronous, Up Direction, CMOS, CDIP16,

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中文翻译

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MC14018BCLS 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：unknown
风险等级：5.38计数方向：UP
JESD-30 代码：R-XDIP-T16JESD-609代码：e0
负载/预设输入：YES逻辑集成电路类型：DECADE COUNTER
工作模式：SYNCHRONOUS功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：CERAMIC
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
电源：5/15 V认证状态：Not Qualified
子类别：Counters表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

MC14018BCLS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 620  
The MC14018B contains five Johnson counter stages which are  
asynchronously presettable and resettable. The counters are synchronous,  
and increment on the positive going edge of the clock.  
P SUFFIX  
PLASTIC  
CASE 648  
Presetting is accomplished by a logic 1 on the preset enable input. Data on  
the Jam inputs will then be transferred to their respective Q outputs  
(inverted). A logic 1 on the reset input will cause all Q outputs to go to a logic  
1 state.  
Division by any number from 2 to 10 can be accomplished by connecting  
appropriate Q outputs to the data input, as shown in the Function Selection  
table. Anti–lock gating is included in the MC14018B to assure proper  
counting sequence.  
D SUFFIX  
SOIC  
CASE 751B  
•
•
•
Fully Static Operation  
Schmitt Trigger on Clock Input  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range  
Pin–for–Pin Replacement for CD4018B  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
•
T
= – 55° to 125°C for all packages.  
A
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
FUNCTIONAL TRUTH TABLE  
V
DD  
– 0.5 to + 18.0  
Preset  
Jam  
V , V  
in out  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
Clock Reset Enable Input  
Qn  
l , l  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
in out  
0
0
0
0
1
0
0
1
1
X
X
X
0
1
X
Qn  
D *  
n
1
0
1
X
X
X
P
D
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
T
stg  
– 65 to + 150  
260  
* D is the Data input for that stage. Stage 1  
n
has Data brought out to Pin 1.  
T
L
Lead Temperature (8–Second Soldering)  
C
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
PIN ASSIGNMENT  
D
1
2
16  
15  
V
DD  
in  
JAM 1  
R
This device contains protection circuitry to guard against damage  
due to high static voltages or electric fields. However, precautions must  
be taken to avoid applications of any voltage higher than maximum rated  
JAM 2  
Q2  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
C
Q5  
voltages to this high-impedance circuit. For proper operation, V and  
in  
V
out  
should be constrained to the range V  
SS  
≤ (V or V ) ≤ V  
in out DD  
.
Q1  
JAM 5  
Q4  
Unused inputs must always be tied to an appropriate logic voltage  
level (e.g., either V or V ). Unused outputs must be left open.  
Q3  
SS DD  
JAM 3  
PE  
V
JAM 4  
SS  
REV 3  
1/94  
Motorola, Inc. 1995  
123456

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