SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14018B contains five Johnson counter stages which are
asynchronously presettable and resettable. The counters are synchronous,
and increment on the positive going edge of the clock.
P SUFFIX
PLASTIC
CASE 648
Presetting is accomplished by a logic 1 on the preset enable input. Data on
the Jam inputs will then be transferred to their respective Q outputs
(inverted). A logic 1 on the reset input will cause all Q outputs to go to a logic
1 state.
Division by any number from 2 to 10 can be accomplished by connecting
appropriate Q outputs to the data input, as shown in the Function Selection
table. Anti–lock gating is included in the MC14018B to assure proper
counting sequence.
D SUFFIX
SOIC
CASE 751B
•
•
•
Fully Static Operation
Schmitt Trigger on Clock Input
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Pin–for–Pin Replacement for CD4018B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
•
T
= – 55° to 125°C for all packages.
A
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
FUNCTIONAL TRUTH TABLE
V
DD
– 0.5 to + 18.0
Preset
Jam
V , V
in out
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
Clock Reset Enable Input
Qn
l , l
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
0
0
0
0
1
0
0
1
1
X
X
X
0
1
X
Qn
D *
n
1
0
1
X
X
X
P
D
Power Dissipation, per Package†
Storage Temperature
500
mW
C
T
stg
– 65 to + 150
260
* D is the Data input for that stage. Stage 1
n
has Data brought out to Pin 1.
T
L
Lead Temperature (8–Second Soldering)
C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
PIN ASSIGNMENT
D
1
2
16
15
V
DD
in
JAM 1
R
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
JAM 2
Q2
3
4
5
6
7
8
14
13
12
11
10
9
C
Q5
voltages to this high-impedance circuit. For proper operation, V and
in
V
out
should be constrained to the range V
SS
≤ (V or V ) ≤ V
in out DD
.
Q1
JAM 5
Q4
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V or V ). Unused outputs must be left open.
Q3
SS DD
JAM 3
PE
V
JAM 4
SS
REV 3
1/94
Motorola, Inc. 1995
MOTOROLA CMOS LOGIC DATA
MC14018B
81