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MC10H644FN

更新时间： 2024-11-19 04:59:39
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器
页数 文件大小 规格书
6页 167K
描述
68030/040 PECL to TTL Clock Driver

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中文翻译

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MC10H644FN 技术参数

是否无铅： 含铅生命周期：Obsolete
零件包装代码：QLCC包装说明：PLASTIC, LCC-20
针数：20Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.45
系列：10H输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-PQCC-J20JESD-609代码：e0
长度：8.965 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
功能数量：1反相输出次数：
端子数量：20实输出次数：4
最高工作温度：85 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC28,.5SQ封装形状：SQUARE
封装形式：CHIP CARRIER电源：5 V
Prop。Delay @ Nom-Sup：7.5 ns传播延迟（tpd）：6.7 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：1.5 ns
座面最大高度：4.57 mm子类别：Clock Drivers
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：ECL温度等级：OTHER
端子面层：Tin/Lead (Sn80Pb20)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：8.965 mm最小 fmax：135 MHz
Base Number Matches：1

MC10H644FN 数据手册

 浏览型号MC10H644FN的Datasheet PDF文件第2页浏览型号MC10H644FN的Datasheet PDF文件第3页浏览型号MC10H644FN的Datasheet PDF文件第4页浏览型号MC10H644FN的Datasheet PDF文件第5页浏览型号MC10H644FN的Datasheet PDF文件第6页 
MC10H644, MC100H644  
68030/040 PECL to TTL  
Clock Driver  
The MC10H/100H644 generates the necessary clocks for the  
68030, 68040 and similar microprocessors. The device is functionally  
equivalent to the H640, but with fewer outputs in a smaller outline  
20−lead PLCC package. It is guaranteed to meet the clock  
specifications required by the 68030 and 68040 in terms of  
part−to−partskew, within−part skew and also duty cycle skew.  
The user has a choice of using either TTL or PECL (ECL referenced  
to +5.0 V) for the input clock. TTL clocks are typically used in present  
MPU systems. However, as clock speeds increase to 50 MHz and  
beyond, the inherent superiority of ECL (particularly differential  
ECL) as a means of clock signal distribution becomes increasingly  
evident. The H644 also uses differential ECL internally to achieve its  
superior skew characteristic.  
The H644 includes divide−by−two and divide−by−four stages, both  
to achieve the necessary duty cycle and skew to generate MPU clocks  
as required. A typical 50 MHz processor application would use an  
input clock running at 100 MHz, thus obtaining output clocks at  
50 MHz and 25 MHz (see Logic Symbol).  
The 10H version is compatible with MECL™ 10H ECL logic levels,  
while the 100H version is compatible with 100K levels (referenced  
to +5.0 V).  
http://onsemi.com  
MARKING  
DIAGRAM  
1
10H644  
PLCC−20  
FN SUFFIX  
CASE 775  
AWLYYWW  
A
= Assembly Location  
= Wafer Lot  
= Year  
WL  
YY  
WW  
= Work Week  
• Generates Clocks for 68030/040  
• Meets 68030/040 Skew Requirements  
• TTL or PECL Input Clock  
• Extra TTL and ECL Power/Ground Pins  
• Within Device Skew on Similar Paths is 0.5 ns  
• Asynchronous Reset  
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC10H644FN  
MC100H644FN  
PLCC−20  
37 Units/Rail  
37 Units/Rail  
PLCC−20  
• Single +5.0 V Supply  
Function  
Reset (R): LOW on RESET forces all Q outputs LOW and all Q  
outputs HIGH.  
Synchronized Outputs: The device is designed to have the POS  
edges of the ÷2 and ÷4 outputs synchronized.  
Select (SEL): LOW selects the PECL input source (DE/DE). HIGH  
selects the TTL input source (DT).  
The H644 also contains circuitry to force a stable state of the PECL  
input differential pair, should both sides be left open. In this case, the  
DE side of the input is pulled LOW, and DE goes HIGH.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
June, 2006 − Rev. 6  
MC10H644/D  
123456

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