SEMICONDUCTOR TECHNICAL DATA
The MC10/100H681 is a dual supply Hex ECL/TTL transceiver with
latches in both directions. ECL controlled Direction and Chip Enable Bar
pins. There are two Latch Enable pins, one for each direction.
The ECL outputs are single ended and drive 50 Ω. The TTL outputs are
specified to source 15 mA and sink 48 mA, allowing the ability to drive highly
capacitive loads. The high driving ability of the TTL outputs make the device
ideal for bussing applications.
The ECL output levels are standard V
and V
cutoff equal to –2.0 V
OH
OL
(V ). When the ECL ports are disabled the outputs go to the V
cutoff
TT OL
level. Multiple ECL V pins are utilized to minimize switching noise.
CCO
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
The TTL ports have standard levels. The TTL input receivers have PNP
input devices to significantly reduce loading. Multiple TTL power and ground
pins are utilized to minimize switching noise.
The 10H version is compatible with MECL 10H ECL logic levels. The
100H version is compatible with 100K levels.
•
•
•
•
Separate Latch Enable Controls for each Direction
ECL Single Ended 50 Ω I/O Port
High Drive TTL I/O Ports
Extra TTL and ECL Power/Ground Pins to Minimize
Switching Noise
•
•
Dual Supply
Direction and Chip Enable Control Pins
Pin
Symbol
Description
1
2
3
TI01
VT
GT
TTL I/O BIT 1
TTL V (5.0 V)
TTL GND (0 V)
CC
4
5
6
7
8
9
TI00
DIR
CEB
LEET
LETE
TTL I/O Bit 0
Pinout: 28–Lead PLCC (Top View)
Direction Control (ECL)
Chip Enable Bar Control (ECL)
Latch Enable ECL-TTL Control (ECL)
Latch Enable TTL-ECL Control (ECL)
ECL Supply (–5.2/–4.5 V)
ECL I/O BIT 0
V
EE
25
24
23
22
21
20
19
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
EI00
EI01
EI02
26
27
28
18
EIO5
TIO2
VT
ECL I/O BIT 1
ECL I/O BIT 2
V
17
16
CCO
V
ECL V
(0 V) — Outputs
CCO
EIO3
CC
TTL I/O BIT 3
ECL V (0 V)
GT
EIO4
V
CCE
EIO4
CC
ECL I/O BIT 4
ECL V (0 V) — Outputs
TIO1
VT
15
14
13
12
V
1
2
CCE
V
CCO
CC
EIO5
TI05
GT
ECL I/O BIT 5
TTL I/O BIT 5
TTL GND (0 V)
EIO3
3
4
V
GT
VT
TI04
GT
TTL V
TTL I/O BIT 4
(5.0 V)
CCO
CC
TIO0
EIO2
TTL GND (0 V)
VT
TTL V
TTL I/O BIT 3
TTL I/O BIT 2
(5.0 V)
CC
5
6
7
8
9
10
11
TIO3
TIO2
VT
TTL V
TTL V
(5.0 V)
(0 V)
CC
CC
GT
9/96
Motorola, Inc. 1996
REV 2
2–316