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MC10H681FNR2 PDF预览

MC10H681FNR2

更新时间: 2024-11-24 04:45:11
品牌 Logo 应用领域
安森美 - ONSEMI 输出元件
页数 文件大小 规格书
8页 186K
描述
HEX TTL TO ECL TRANSCEIVER, TRUE OUTPUT, PQCC28, PLASTIC, LCC-28

MC10H681FNR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-28
针数:28Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.3最大延迟:7.8 ns
接口集成电路类型:TTL TO ECL TRANSCEIVERJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.505 mm
湿度敏感等级:1标称负供电电压:-5.2 V
位数:1功能数量:6
端子数量:28最高工作温度:75 °C
最低工作温度:输出特性:3-STATE
输出锁存器或寄存器:LATCH输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
认证状态:Not Qualified座面最大高度:4.57 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn80Pb20)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:11.505 mmBase Number Matches:1

MC10H681FNR2 数据手册

 浏览型号MC10H681FNR2的Datasheet PDF文件第2页浏览型号MC10H681FNR2的Datasheet PDF文件第3页浏览型号MC10H681FNR2的Datasheet PDF文件第4页浏览型号MC10H681FNR2的Datasheet PDF文件第5页浏览型号MC10H681FNR2的Datasheet PDF文件第6页浏览型号MC10H681FNR2的Datasheet PDF文件第7页 
MC10H681, MC100H681  
Hex ECL to TTL Transceiver  
with Latches  
The MC10/100H681 is a dual supply Hex ECL/TTL transceiver  
with latches in both directions. ECL controlled Direction and Chip  
Enable Bar pins. There are two Latch Enable pins, one for each  
direction.  
The ECL outputs are single ended and drive 50 W. The TTL outputs  
are specified to source 15 mA and sink 48 mA, allowing the ability to  
drive highly capacitive loads. The high driving ability of the TTL  
outputs make the device ideal for bussing applications.  
http://onsemi.com  
MARKING  
DIAGRAM  
1
The ECL output levels are standard V and V cutoff equal to  
OH  
OL  
2.0 V (V ). When the ECL ports are disabled the outputs go to the  
TT  
10H681  
V
OL  
cutoff level. Multiple ECL V  
pins are utilized to minimize  
PLCC28  
FN SUFFIX  
CASE 776  
CCO  
AWLYYWW  
switching noise.  
The TTL ports have standard levels. The TTL input receivers have  
PNP input devices to significantly reduce loading. Multiple TTL  
power and ground pins are utilized to minimize switching noise.  
The 10H version is compatible with MECL10H ECL logic levels.  
The 100H version is compatible with 100K levels.  
A
= Assembly Location  
WL  
YY  
WW  
= Wafer Lot  
= Year  
= Work Week  
Separate Latch Enable Controls for each Direction  
ECL Single Ended 50 W I/O Port  
High Drive TTL I/O Ports  
Extra TTL and ECL Power/Ground Pins to Minimize Switching  
Noise  
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC10H681FN  
MC100H681FN  
PLCC28  
37 Units/Rail  
37 Units/Rail  
Dual Supply  
Direction and Chip Enable Control Pins  
PLCC28  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
June, 2006 Rev. 5  
MC10H681/D  

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