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MC10H680FNR2G PDF预览

MC10H680FNR2G

更新时间: 2024-11-19 03:41:03
品牌 Logo 应用领域
安森美 - ONSEMI 总线收发器转换器电平转换器驱动程序和接口锁存器接口集成电路
页数 文件大小 规格书
10页 138K
描述
4−Bit Differential ECL Bus to TTL Bus Transceiver

MC10H680FNR2G 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-28
针数:28Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.19
最大延迟:4.8 ns接口集成电路类型:TTL TO ECL TRANSCEIVER
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.505 mm标称负供电电压:-5.2 V
位数:1功能数量:4
端子数量:28最高工作温度:75 °C
最低工作温度:输出特性:3-STATE
输出锁存器或寄存器:NONE输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:4.57 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:11.505 mmBase Number Matches:1

MC10H680FNR2G 数据手册

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MC10H680, MC100H680  
4−Bit Differential ECL Busꢀ  
to TTL Bus Transceiver  
Description  
The MC10H/100H680 is a dual supply 4bit differential ECL bus to  
TTL bus transceiver. It is designed to allow the system designer to no  
longer be limited in bus speed associated with standard TTL busses.  
Using a differential ECL Bus will increase the frequency of operation  
and increase noise immunity.  
http://onsemi.com  
Both the TTL and the ECL ports are capable of driving a bus. The  
ECL outputs have the ability to drive 25 W, allowing both ends of the  
bus line to be terminated in the characteristic impedance of 50 W. The  
TTL outputs are specified to source 15 mA and sink 48 mA, allowing  
the ability to drive highly capacitive loads.  
PLCC28  
FN SUFFIX  
CASE 776  
The ECL output levels are V approximately equal to 1.0 V and  
OH  
V
OL  
cutoff equal to 2.0 V (VTT). When the ECL ports are disabled  
both EIOx and EIOxB go to the V cutoff level. The ECL input  
OL  
receivers have special circuitry which detects this disabled condition,  
prevents oscillation, and forces the TTL output to the low state. The  
noise margin in this disabled state is greater than 600 mV. Multiple  
MARKING DIAGRAM*  
ECL V  
pins are utilized to minimize switching noise.  
CCO  
1
The TTL ports have standard levels. The TTL input receivers have  
PNP input devices to significantly reduce loading. Multiple TTL  
power and ground pins are utilized to minimize switching noise.  
The control pins (EDIR and ECEB) of the 10H version is  
compatible with MECL 10HECL logic levels. The control pins of  
the 100H version are compatible with 100K levels.  
MCxxxH680G  
AWLYYWW  
Features  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
Differential ECL Bus (25 W) I/O Ports  
High Drive TTL Bus I/O Ports  
Extra TTL and ECL Power/Ground Pins to Minimize  
Switching Noise  
Dual Supply  
Direction and Chip Enable Control Pins  
PbFree Packages are Available*  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 Rev. 11  
MC10H680/D  

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