Datasheet > MC10H644_06

MC10H644_06

更新时间： 2024-11-19 04:59:39

品牌	Logo	应用领域
安森美 - ONSEMI		时钟驱动器
页数	文件大小	规格书
6页	167K
描述
68030/040 PECL to TTL Clock Driver

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MC10H644_06 数据手册

MC10H644, MC100H644

68030/040 PECL to TTL

Clock Driver

The MC10H/100H644 generates the necessary clocks for the

68030, 68040 and similar microprocessors. The device is functionally

equivalent to the H640, but with fewer outputs in a smaller outline

20−lead PLCC package. It is guaranteed to meet the clock

specifications required by the 68030 and 68040 in terms of

part−to−partskew, within−part skew and also duty cycle skew.

The user has a choice of using either TTL or PECL (ECL referenced

to +5.0 V) for the input clock. TTL clocks are typically used in present

MPU systems. However, as clock speeds increase to 50 MHz and

beyond, the inherent superiority of ECL (particularly differential

ECL) as a means of clock signal distribution becomes increasingly

evident. The H644 also uses differential ECL internally to achieve its

superior skew characteristic.

The H644 includes divide−by−two and divide−by−four stages, both

to achieve the necessary duty cycle and skew to generate MPU clocks

as required. A typical 50 MHz processor application would use an

input clock running at 100 MHz, thus obtaining output clocks at

50 MHz and 25 MHz (see Logic Symbol).

The 10H version is compatible with MECL™ 10H ECL logic levels,

while the 100H version is compatible with 100K levels (referenced

to +5.0 V).

http://onsemi.com

MARKING

DIAGRAM

10H644

PLCC−20

FN SUFFIX

CASE 775

AWLYYWW

= Assembly Location

= Wafer Lot

= Year

= Work Week

• Generates Clocks for 68030/040

• Meets 68030/040 Skew Requirements

• TTL or PECL Input Clock

• Extra TTL and ECL Power/Ground Pins

• Within Device Skew on Similar Paths is 0.5 ns

• Asynchronous Reset

ORDERING INFORMATION

Device

Package

Shipping

MC10H644FN

MC100H644FN

PLCC−20

37 Units/Rail

PLCC−20

• Single +5.0 V Supply

Function

Reset (R): LOW on RESET forces all Q outputs LOW and all Q

outputs HIGH.

Synchronized Outputs: The device is designed to have the POS

edges of the ÷2 and ÷4 outputs synchronized.

Select (SEL): LOW selects the PECL input source (DE/DE). HIGH

selects the TTL input source (DT).

The H644 also contains circuitry to force a stable state of the PECL

input differential pair, should both sides be left open. In this case, the

DE side of the input is pulled LOW, and DE goes HIGH.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

June, 2006 − Rev. 6

MC10H644/D

12 3 4 5 6

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与MC10H644_06相关器件

型号	品牌	获取价格	描述	数据表
MC10H644FN	ONSEMI	获取价格	68030/040 PECL to TTL Clock Driver
MC10H644FN	MOTOROLA	获取价格	68030/040 PECL-TTL CLOCK DRIVER
MC10H644FNR2	MOTOROLA	获取价格	10H SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC20, PLASTIC
MC10H645	ONSEMI	获取价格	1:9 TTL CLOCK DRIVER
MC10H645_06	ONSEMI	获取价格	1:9 TTL Clock Driver
MC10H645FN	ONSEMI	获取价格	1:9 TTL Clock Driver
MC10H645FNG	ONSEMI	获取价格	1:9 TTL Clock Driver
MC10H645FNR2	ONSEMI	获取价格	1:9 TTL Clock Driver
MC10H645FNR2G	ONSEMI	获取价格	1:9 TTL Clock Driver
MC10H646	ONSEMI	获取价格	PENTIUM MICROPROCESSOR PECL/TTL-TTL CLOCK DRIVER

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