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MC10H016 PDF预览

MC10H016

更新时间: 2024-09-05 22:39:47
品牌 Logo 应用领域
安森美 - ONSEMI 计数器
页数 文件大小 规格书
4页 144K
描述
4-Bit Binary Counter

MC10H016 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10H016 is a high–speed synchronous, presettable, cascadable  
4–bit binary counter. It is useful for a large number of conversion, counting and  
digital integration applications.  
Counting Frequency, 200 MHz Minimum  
Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
Voltage Compensated  
MECL 10K–Compatible  
Positive Edge Triggered  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
MAXIMUM RATINGS  
Characteristic  
= 0)  
Symbol  
Rating  
Unit  
Vdc  
Vdc  
mA  
Power Supply (V  
Input Voltage (V  
V
–8.0 to 0  
FN SUFFIX  
PLCC  
CASE 775–02  
CC  
= 0)  
EE  
V
I
0 to V  
EE  
CC  
Output Current — Continuous  
— Surge  
I
50  
100  
out  
Operating Temperature Range  
T
A
0 to +75  
°C  
°C  
Storage Temperature Range — Plastic  
— Ceramic  
T
–55 to +150  
–55 to +165  
stg  
DIP  
PIN ASSIGNMENT  
ELECTRICAL CHARACTERISTICS (V  
= –5.2 V ±5%) (See Note)  
EE  
0°  
25°  
75°  
V
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
Characteristic  
Symbol  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
Q2  
Q3  
CP  
MR  
P3  
P2  
P1  
Power Supply Current  
I
126  
115  
126  
mA  
Q1  
E
Input Current High  
All Except MR  
Pin 12 MR  
I
µA  
inH  
Q0  
TC  
PE  
CE  
PO  
450  
1190  
265  
700  
265  
700  
Input Current Low  
High Output Voltage  
Low Output Voltage  
High Input Voltage  
Low Input Voltage  
I
0.5  
0.5  
0.3  
µA  
inL  
V
–1.02 –0.84 –0.98 –0.81 –0.92  
–1.95 –1.63 –1.95 –1.63 –1.95  
–1.17 –0.84 –1.13 –0.81 –1.07  
–1.95 –1.48 –1.95 –1.48 –1.95  
–0.735  
–1.60  
Vdc  
Vdc  
Vdc  
Vdc  
OH  
V
OL  
V
–0.735  
–1.45  
IH  
V
IL  
V
EE  
AC PARAMETERS  
Propagation Delay  
Clock to Q  
Clock to TC  
MR to Q  
t
ns  
pd  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
1.0  
0.7  
0.7  
2.4  
2.4  
2.4  
1.0  
0.7  
0.7  
2.5  
2.5  
2.5  
1.0  
0.7  
0.7  
2.7  
2.6  
2.6  
Set–up Time  
t
ns  
ns  
set  
P
to Clock  
2.0  
2.5  
2.0  
2.5  
2.0  
2.5  
n
CE or PE to Clock  
TRUTH TABLE  
Hold Time  
Clock to P  
n
Clock to CE or PE  
Counting Frequency  
Rise Time  
t
hold  
1.0  
0.5  
1.0  
0.5  
1.0  
0.5  
CE PE MR CP  
Function  
f
200  
0.5  
0.5  
200  
0.5  
0.5  
200  
0.5  
0.5  
MHz  
ns  
count  
L
H
L
H
X
L
L
H
H
X
L
L
L
L
L
Z
Z
Z
Z
Load Parallel (P to Q )  
n
n
Load Parallel (P to Q )  
t
2.0  
2.0  
2.1  
2.1  
2.2  
2.2  
n
n
r
Count  
Hold  
Fall Time  
t
f
ns  
ZZ Masters Respond;  
Slaves Hold  
NOTE:  
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,  
afterthermalequilibriumhasbeenestablished.Thecircuitisinatestsocketormountedonaprintedcircuit  
board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a  
50–ohm resistor to –2.0 volts.  
X
X
H
X
Reset (Q = LOW,  
n
T
= HIGH)  
C
Z = Clock Pulse (Low to High); ZZ = Clock Pulse (High to Low)  
Features include assertion inputs and outputs on each  
of the four master/slave counting flip–flops. Terminal  
count is generated internally in a manner that allows  
synchronous loading at nearly the speed of the basic  
counter.  
9/96  
Motorola, Inc. 1996  
REV 6  

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