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MC10H016FN

更新时间： 2024-09-05 22:34:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器触发器逻辑集成电路输出元件
页数 文件大小 规格书
4页 144K
描述
4-Bit Binary Counter

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中文翻译

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MC10H016FN 技术参数

生命周期：Transferred零件包装代码：QLCC
包装说明：QCCJ, LDCC20,.4SQ针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.44Is Samacsys：N
其他特性：TCO OUTPUT计数方向：UP
系列：10HJESD-30 代码：S-PQCC-J20
JESD-609代码：e0长度：8.965 mm
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：200000000 Hz工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：20最高工作温度：75 °C
最低工作温度：输出特性：OPEN-EMITTER
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC20,.4SQ封装形状：SQUARE
封装形式：CHIP CARRIER最大电源电流（ICC）：126 mA
传播延迟（tpd）：2.7 ns认证状态：Not Qualified
座面最大高度：4.57 mm子类别：Counters
表面贴装：YES技术：ECL
温度等级：COMMERCIAL EXTENDED端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD触发器类型：POSITIVE EDGE
宽度：8.965 mm最小 fmax：200 MHz
Base Number Matches：1

MC10H016FN 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10H016 is a high–speed synchronous, presettable, cascadable  
4–bit binary counter. It is useful for a large number of conversion, counting and  
digital integration applications.  
•
•
Counting Frequency, 200 MHz Minimum  
Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
•
•
•
Voltage Compensated  
MECL 10K–Compatible  
Positive Edge Triggered  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
MAXIMUM RATINGS  
Characteristic  
= 0)  
Symbol  
Rating  
Unit  
Vdc  
Vdc  
mA  
Power Supply (V  
Input Voltage (V  
V
–8.0 to 0  
FN SUFFIX  
PLCC  
CASE 775–02  
CC  
= 0)  
EE  
V
I
0 to V  
EE  
CC  
Output Current — Continuous  
— Surge  
I
50  
100  
out  
Operating Temperature Range  
T
A
0 to +75  
°C  
°C  
Storage Temperature Range — Plastic  
— Ceramic  
T
–55 to +150  
–55 to +165  
stg  
DIP  
PIN ASSIGNMENT  
ELECTRICAL CHARACTERISTICS (V  
= –5.2 V ±5%) (See Note)  
EE  
0°  
25°  
75°  
V
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
Characteristic  
Symbol  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
Q2  
Q3  
CP  
MR  
P3  
P2  
P1  
Power Supply Current  
I
—
126  
—
115  
—
126  
mA  
Q1  
E
Input Current High  
All Except MR  
Pin 12 MR  
I
µA  
inH  
Q0  
TC  
PE  
CE  
PO  
—
—
450  
1190  
—
—
265  
700  
—
—
265  
700  
Input Current Low  
High Output Voltage  
Low Output Voltage  
High Input Voltage  
Low Input Voltage  
I
0.5  
—
0.5  
—
0.3  
—
µA  
inL  
V
–1.02 –0.84 –0.98 –0.81 –0.92  
–1.95 –1.63 –1.95 –1.63 –1.95  
–1.17 –0.84 –1.13 –0.81 –1.07  
–1.95 –1.48 –1.95 –1.48 –1.95  
–0.735  
–1.60  
Vdc  
Vdc  
Vdc  
Vdc  
OH  
V
OL  
V
–0.735  
–1.45  
IH  
V
IL  
V
EE  
AC PARAMETERS  
Propagation Delay  
Clock to Q  
Clock to TC  
MR to Q  
t
ns  
pd  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
1.0  
0.7  
0.7  
2.4  
2.4  
2.4  
1.0  
0.7  
0.7  
2.5  
2.5  
2.5  
1.0  
0.7  
0.7  
2.7  
2.6  
2.6  
Set–up Time  
t
ns  
ns  
set  
P
to Clock  
2.0  
2.5  
—
—
2.0  
2.5  
—
—
2.0  
2.5  
—
—
n
CE or PE to Clock  
TRUTH TABLE  
Hold Time  
Clock to P  
n
Clock to CE or PE  
Counting Frequency  
Rise Time  
t
hold  
1.0  
0.5  
—
—
1.0  
0.5  
—
—
1.0  
0.5  
—
—
CE PE MR CP  
Function  
f
200  
0.5  
0.5  
—
200  
0.5  
0.5  
—
200  
0.5  
0.5  
—
MHz  
ns  
count  
L
H
L
H
X
L
L
H
H
X
L
L
L
L
L
Z
Z
Z
Z
Load Parallel (P to Q )  
n
n
Load Parallel (P to Q )  
t
2.0  
2.0  
2.1  
2.1  
2.2  
2.2  
n
n
r
Count  
Hold  
Fall Time  
t
f
ns  
ZZ Masters Respond;  
Slaves Hold  
NOTE:  
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,  
afterthermalequilibriumhasbeenestablished.Thecircuitisinatestsocketormountedonaprintedcircuit  
board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a  
50–ohm resistor to –2.0 volts.  
X
X
H
X
Reset (Q = LOW,  
n
T
= HIGH)  
C
Z = Clock Pulse (Low to High); ZZ = Clock Pulse (High to Low)  
Features include assertion inputs and outputs on each  
of the four master/slave counting flip–flops. Terminal  
count is generated internally in a manner that allows  
synchronous loading at nearly the speed of the basic  
counter.  
9/96  
Motorola, Inc. 1996  
REV 6  
1234

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