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MC10114FNR2 PDF预览

MC10114FNR2

更新时间： 2024-09-15 19:43:07
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 接口集成电路
页数 文件大小 规格书
8页 109K
描述
Line Receiver, 3 Func, 3 Rcvr, ECL, PQCC20, PLASTIC, LCC-20

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MC10114FNR2 技术参数

生命周期：Contact Manufacturer包装说明：QCCJ,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.65
差分输出：YES输入特性：DIFFERENTIAL
接口集成电路类型：LINE RECEIVER接口标准：GENERAL PURPOSE
JESD-30 代码：S-PQCC-J20JESD-609代码：e0
长度：8.965 mm标称负供电电压：-5.2 V
功能数量：3端子数量：20
最高工作温度：85 °C最低工作温度：-30 °C
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
最大接收延迟：4 ns接收器位数：3
座面最大高度：4.57 mm表面贴装：YES
技术：ECL温度等级：OTHER
端子面层：TIN LEAD端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：8.965 mmBase Number Matches：1

MC10114FNR2 数据手册

 浏览型号MC10114FNR2的Datasheet PDF文件第2页浏览型号MC10114FNR2的Datasheet PDF文件第3页浏览型号MC10114FNR2的Datasheet PDF文件第4页浏览型号MC10114FNR2的Datasheet PDF文件第5页浏览型号MC10114FNR2的Datasheet PDF文件第6页浏览型号MC10114FNR2的Datasheet PDF文件第7页 
MC10114  
Triple Line Receiver  
The MC10114 is a triple line receiver designed for use in sensing  
differential signals over long lines. An active current source and  
translated emitter follower inputs provide the line receiver with a  
common mode noise rejection limit of one volt in either the positive or  
the negative direction. This allows a large amount of common mode  
noise immunity for extra long lines.  
http://onsemi.com  
Another feature of the MC10114 is that the OR outputs go to a logic  
low level whenever the inputs are left floating. The outputs are each  
capable of driving 50 ohm transmission lines.  
This device is useful in high speed central processors,  
minicomputers, peripheral controllers, digital communication  
systems, testing and instrumen– tation systems. The MC10114 can  
also be used for MOS to MECL interfacing and it is ideal as a sense  
amplifier for MOS RAM’s.  
MARKING  
DIAGRAMS  
16  
CDIP–16  
L SUFFIX  
CASE 620  
MC10114L  
AWLYYWW  
1
A V  
reference is provided which is useful in making the  
BB  
16  
MC10114 a Schmit trigger, allowing single–ended driving of the  
inputs, or other applications where a stable reference voltage is  
necessary. See MECL Design Handbook (HB205) pages 226 and 228.  
PDIP–16  
P SUFFIX  
CASE 648  
MC10114P  
AWLYYWW  
1
• P = 145 mW typ/pkg  
D
1
• t = 2.4 ns typ (Single Ended Input)  
pd  
• t = 2.0 ns typ (Differential Input)  
PLCC–20  
FN SUFFIX  
CASE 775  
pd  
10114  
• t , t = 2.1 ns typ (20%–80%)  
r
f
AWLYYWW  
LOGIC DIAGRAM  
4
5
2
3
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
9
6
7
10  
12  
13  
14  
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
ORDERING INFORMATION  
CC2  
15  
11  
V
EE  
Device  
Package  
Shipping  
V
BB  
*
*V to be used to supply bias to the MC10114 only and bypassed (when used) with  
BB  
MC10114L  
CDIP–16  
25 Units / Rail  
0.01 µF to 0.1 µF capacitor to ground (0 V). V can source < 1.0 mA.  
BB  
When the input pin with the bubble goes positive, its respective output pin with  
bubble goes positive.  
MC10114P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
DIP PIN ASSIGNMENT  
MC10114FN  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
V
CC2  
CC1  
OUT  
OUT  
A
A
C
C
C
C
V
OUT  
OUT  
IN  
A
IN  
A
IN  
IN  
B
OUT  
B
OUT  
BB  
IN  
B
B
V
IN  
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables on page 18  
of the ON Semiconductor MECL Data Book (DL122/D).  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10114/D  
12345678

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