Datasheet > MC100LVEL14_06

MC100LVEL14_06

更新时间： 2024-02-15 23:48:06

品牌	Logo	应用领域
安森美 - ONSEMI		时钟
页数	文件大小	规格书
6页	128K
描述
3.3V ECL 1:5 Clock Distribution Chip

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MC100LVEL14_06 数据手册

MC100LVEL14

3.3VꢀECL 1:5 Clock

Distribution Chip

Description

The MC100LVEL14 is a low skew 1:5 clock distribution chip

designed explicitly for low skew clock distribution applications. The

device can be driven by either a differential or single-ended ECL or, if

positive power supplies are used, PECL input signal. The LVEL14 is

functionally and pin compatible with the EL14 but is designed to

operate in ECL or PECL mode for a voltage supply range of −3.0 V to

−3.8 V ( or 3.0 V to 3.8 V).

http://onsemi.com

MARKING

DIAGRAM

The LVEL14 features a multiplexed clock input to allow for the

distribution of a lower speed scan or test clock along with the high speed

system clock. When LOW (or left open and pulled LOW by the input

pulldown resistor) the SEL pin will select the differential clock input.

The common enable (EN) is synchronous so that the outputs will only

be enabled/disabled when they are already in the LOW state. This

avoids any chance of generating a runt clock pulse when the device is

enabled/disabled as can happen with an asynchronous control. The

internal flip flop is clocked on the falling edge of the input clock,

therefore all associated specification limits are referenced to the

negative edge of the clock input.

100LVEL14

AWLYYWWG

SOIC−20

DW SUFFIX

CASE 751D

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

The V pin, an internally generated voltage supply, is available to

this device only. For single−ended input conditions, the unused

differential input is connected to V as a switching reference voltage.

may also rebias AC coupled inputs. When used, decouple V and

via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

mA. When not used, V should be left open.

Features

• 50 ps Output-to-Output Skew

• Synchronous Enable/Disable

• Multiplexed Clock Input

• ESD Protection: Human Body Model >2 kV

• The 100 Series Contains Temperature Compensation

• PECL Mode Operating Range:

= 3.0 V to 3.8 V with V = 0 V

• NECL Mode Operating Range:

= 0 V with V = −3.0 V to −3.8 V

• Internal Input Pulldown Resistors on CLK

• Q Output will Default LOW with Inputs Open or at V

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

• Moisture Sensitivity Level 1

For Additional Information, see Application Note AND8003/D

• Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

• Transistor Count = 303 devices

• Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

November, 2006 − Rev. 8

MC100LVEL14/D

12 3 4 5 6

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与MC100LVEL14_06相关器件

型号	品牌	获取价格	描述	数据表
MC100LVEL14DW	ONSEMI	获取价格	1:5 Clock Distribution Chip
MC100LVEL14DW	MOTOROLA	获取价格	1:5 Clock Distribution Chip
MC100LVEL14DWG	ONSEMI	获取价格	3.3V ECL 1:5 Clock Distribution Chip
MC100LVEL14DWR2	ONSEMI	获取价格	3.3V ECL 1:5 Clock Distribution Chip
MC100LVEL14DWR2G	ONSEMI	获取价格	3.3V ECL 1:5 Clock Distribution Chip
MC100LVEL16	ADI	获取价格	14-Bit, 80 MSPS/105 MSPS A/D Converter
MC100LVEL16	ONSEMI	获取价格	Differential Receiver
MC100LVEL16_06	ONSEMI	获取价格	3.3V ECL Differential Receiver
MC100LVEL16D	ONSEMI	获取价格	3.3V ECL Differential Receiver
MC100LVEL16D	MOTOROLA	获取价格	Differential Receiver

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