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MC100LVEL14DWG PDF预览

MC100LVEL14DWG

更新时间： 2024-01-13 00:44:08
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 128K
描述
3.3V ECL 1:5 Clock Distribution Chip

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中文翻译

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MC100LVEL14DWG 技术参数

是否无铅： 含铅生命周期：Active
零件包装代码：SOIC包装说明：LEAD FREE, SOIC-20
针数：20Reach Compliance Code：unknown
风险等级：5.72其他特性：NECL MODE: VCC = 0V WITH VEE = -3V TO -3.8V
系列：100LVEL输入调节：DIFFERENTIAL MUX
JESD-30 代码：R-PDSO-G20JESD-609代码：e3
长度：12.8 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
湿度敏感等级：NOT SPECIFIED功能数量：1
反相输出次数：端子数量：20
实输出次数：5最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
传播延迟（tpd）：0.83 ns认证状态：COMMERCIAL
Same Edge Skew-Max（tskwd）：0.05 ns座面最大高度：2.65 mm
最大供电电压 (Vsup)：3.8 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：ECL温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：7.5 mm
Base Number Matches：1

MC100LVEL14DWG 数据手册

 浏览型号MC100LVEL14DWG的Datasheet PDF文件第2页浏览型号MC100LVEL14DWG的Datasheet PDF文件第3页浏览型号MC100LVEL14DWG的Datasheet PDF文件第4页浏览型号MC100LVEL14DWG的Datasheet PDF文件第5页浏览型号MC100LVEL14DWG的Datasheet PDF文件第6页 
MC100LVEL14  
3.3VꢀECL 1:5 Clock  
Distribution Chip  
Description  
The MC100LVEL14 is a low skew 1:5 clock distribution chip  
designed explicitly for low skew clock distribution applications. The  
device can be driven by either a differential or single-ended ECL or, if  
positive power supplies are used, PECL input signal. The LVEL14 is  
functionally and pin compatible with the EL14 but is designed to  
operate in ECL or PECL mode for a voltage supply range of −3.0 V to  
−3.8 V ( or 3.0 V to 3.8 V).  
http://onsemi.com  
MARKING  
DIAGRAM  
20  
The LVEL14 features a multiplexed clock input to allow for the  
distribution of a lower speed scan or test clock along with the high speed  
system clock. When LOW (or left open and pulled LOW by the input  
pulldown resistor) the SEL pin will select the differential clock input.  
The common enable (EN) is synchronous so that the outputs will only  
be enabled/disabled when they are already in the LOW state. This  
avoids any chance of generating a runt clock pulse when the device is  
enabled/disabled as can happen with an asynchronous control. The  
internal flip flop is clocked on the falling edge of the input clock,  
therefore all associated specification limits are referenced to the  
negative edge of the clock input.  
20  
100LVEL14  
AWLYYWWG  
1
SOIC−20  
DW SUFFIX  
CASE 751D  
1
A
= Assembly Location  
= Wafer Lot  
WL  
YY  
WW  
G
= Year  
= Work Week  
= Pb−Free Package  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single−ended input conditions, the unused  
differential input is connected to V as a switching reference voltage.  
BB  
V
V
may also rebias AC coupled inputs. When used, decouple V and  
via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5  
BB  
BB  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
CC  
mA. When not used, V should be left open.  
Features  
BB  
• 50 ps Output-to-Output Skew  
• Synchronous Enable/Disable  
• Multiplexed Clock Input  
• ESD Protection: Human Body Model >2 kV  
• The 100 Series Contains Temperature Compensation  
• PECL Mode Operating Range:  
V
CC  
= 3.0 V to 3.8 V with V = 0 V  
EE  
• NECL Mode Operating Range:  
= 0 V with V = −3.0 V to −3.8 V  
V
CC  
EE  
• Internal Input Pulldown Resistors on CLK  
• Q Output will Default LOW with Inputs Open or at V  
EE  
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test  
• Moisture Sensitivity Level 1  
For Additional Information, see Application Note AND8003/D  
• Flammability Rating: UL 94 V−0 @ 0.125 in,  
Oxygen Index: 28 to 34  
• Transistor Count = 303 devices  
• Pb−Free Packages are Available*  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 8  
MC100LVEL14/D  
123456

中文翻译

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MC100LVEL14DWG 替代型号

型号 品牌 替代类型 描述 数据表
MC100LVEL14DWR2G ONSEMI

完全替代

 3.3V ECL 1:5 Clock Distribution Chip
MC100EP809FAG ONSEMI

功能相似

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NB2305AI1DG ONSEMI

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 3.3 V Zero Delay Clock Buffer

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