MC100LVE111
3.3VĄECL 1:9 Differential
Clock Driver
The MC100LVE111 is a low skew 1-to-9 differential driver, designed
with clock distribution in mind. The MC100LVE111’s function and
performance are similar to the popular MC100E111, with the added
feature of low voltage operation. It accepts one signal input, which can be
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either differential or single-ended if the V output is used. The signal is
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fanned out to 9 identical differential outputs.
MARKING
DIAGRAM*
The LVE111 is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize gate
to gate skew within a device, and empirical modeling is used to determine
128
process control limits that ensure consistent t distributions from lot to
pd
lot. The net result is a dependable, guaranteed low skew device.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50 Ω, even if only
one side is being used. In most applications, all nine differential pairs will
be used and therefore terminated. In the case where fewer than nine pairs
are used, it is necessary to terminate at least the output pairs on the same
package side as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of
propagation delay (on the order of 10–20 ps) of the output(s) being used
which, while not being catastrophic to most designs, will mean a loss of
skew margin.
MC100LVE111
AWLYYWW
PLCC–28
FN SUFFIX
CASE 776
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
The MC100LVE111, as with most other ECL devices, can be operated
from a positive V
supply in PECL mode. This allows the LVE111 to
CC
*For additional information, see Application Note
AND8002/D
be used for high performance clock distribution in +3.3 V systems.
Designers can take advantage of the LVE111’s performance to distribute
low skew clocks across the backplane or the board. In a PECL
environment, series or Thevenin line terminations are typically used as
they require no additional power supplies. For systems incorporating
GTL, parallel termination offers the lowest power by taking advantage of
the 1.2 V supply as a terminating voltage. For more information on using
PECL, designers should refer to Application Note AN1406/D.
ORDERING INFORMATION
Device
Package
Shipping
MC100LVE111FN
PLCC–28
37 Units/Rail
The V pin, an internally generated voltage supply, is available to this
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device only. For single-ended input conditions, the unused differential
MC100LVE111FNR2 PLCC–28 500 Units/Reel
input is connected to V as a switching reference voltage. V may also
BB BB
rebias AC coupled inputs. When used, decouple V and V via a 0.01
BB CC
mF capacitor and limit current sourcing or sinking to 0.5 mA. When not
used, V should be left open.
BB
• 200 ps Part-to-Part Skew
• 50 ps Output-to-Output Skew
• ESD Protection: >2 KV HBM, >200 V MM
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V
3.0 V to 3.8 V with V = 0 V
CC=
EE
• NECL Mode Operating Range: V
CC=
• Internal Input Pulldown Resistors
• Q Output will Default LOW with Inputs Open or at V
0 V with V
EE =
–3.0 V to –3.8 V
EE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 250 devices
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
April, 2002 – Rev. 5
MC100LVE111/D
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