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MC100EP91DW PDF预览

MC100EP91DW

更新时间： 2024-01-27 04:51:53
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器驱动程序和接口锁存器接口集成电路光电二极管
页数 文件大小 规格书
10页 168K
描述
2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator

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中文翻译

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MC100EP91DW 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：QFN包装说明：HVQCCN, LCC24,.16SQ,20
针数：24Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：1.79Is Samacsys：N
最大延迟：0.75 ns接口集成电路类型：ECL TO PECL TRANSLATOR
JESD-30 代码：S-XQCC-N24JESD-609代码：e3
长度：4 mm湿度敏感等级：1
位数：1功能数量：3
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出锁存器或寄存器：NONE
输出极性：COMPLEMENTARY封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC24,.16SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：2.5/3.3,-3.3/-5 V
认证状态：Not Qualified座面最大高度：1 mm
子类别：Other Interface ICs最大供电电压：3.8 V
最小供电电压：2.375 V标称供电电压：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：4 mm
Base Number Matches：1

MC100EP91DW 数据手册

 浏览型号MC100EP91DW的Datasheet PDF文件第2页浏览型号MC100EP91DW的Datasheet PDF文件第3页浏览型号MC100EP91DW的Datasheet PDF文件第4页浏览型号MC100EP91DW的Datasheet PDF文件第5页浏览型号MC100EP91DW的Datasheet PDF文件第6页浏览型号MC100EP91DW的Datasheet PDF文件第7页 
MC100EP91  
2.5 V/3.3 V Any Level  
Positive Input to  
−3.3 V/−5.5 V NECL Output  
Translator  
http://onsemi.com  
MARKING DIAGRAMS*  
Description  
The MC100EP91 is a triple any level positive input to NECL output  
translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL,  
CML or LVDS signals, and translates them to differential NECL  
output signals (−3.0 V / −5.5 V).  
20  
20  
MC100EP91  
AWLYYWWG  
1
To accomplish the level translation the EP91 requires three power  
rails. The V pins should be connected to the positive power supply,  
CC  
SO−20 WB  
DW SUFFIX  
CASE 751D  
and the V pin should be connected to the negative power supply.  
EE  
The GND pins are connected to the system ground plane. Both V  
1
EE  
and V should be bypassed to ground via 0.01 mF capacitors.  
CC  
Under open input conditions, the D input will be biased at V /2  
CC  
and the D input will be pulled to GND. These conditions will force the  
Q outputs to a low state, and Q outputs to a high state, which will  
ensure stability.  
24  
1
100  
EP91  
ALYWG  
G
24  
1
The V pin, an internally generated voltage supply, is available to  
BB  
24 PIN QFN  
MN SUFFIX  
CASE 485L  
this device only. For single-ended input conditions, the unused  
differential input is connected to V as a switching reference voltage.  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
A
= Assembly Location  
= Year  
CC  
WL, L = Wafer Lot  
YY, Y  
to 0.5 mA. When not used, V should be left open.  
BB  
WW, W = Work Week  
Features  
G or G = Pb−Free Package  
• Maximum Input Clock Frequency > 2.0 GHz Typical  
• Maximum Input Data Rate > 2.0 Gb/s Typical  
• 500 ps Typical Propagation Delay  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
• Operating Range: V = 2.375 V to 3.8 V;  
CC  
V
EE  
= −3.0 V to −5.5 V; GND = 0 V  
• Q Output will Default LOW with Inputs Open or at GND  
• Pb−Free Packages are Available*  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
August, 2006 − Rev. 1  
MC100EP91/D  
1234567...10

中文翻译

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MC100EP91DW 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP91DWR2G ONSEMI

完全替代

 2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator
MC100EP91DWG ONSEMI

完全替代

 2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator
MC100EP91DWR2 ONSEMI

功能相似

 2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator

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