Datasheet > MC100EL14

MC100EL14

更新时间： 2024-11-19 22:46:23

品牌	Logo	应用领域
安森美 - ONSEMI		时钟
页数	文件大小	规格书
4页	104K
描述
1:5 Clock Distribution Chip

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MC100EL14 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC100LVEL/100EL14 is a low skew 1:5 clock distribution chip

designed explicitly for low skew clock distribution applications. The

device can be driven by either a differential or single-ended ECL or, if

positive power supplies are used, PECL input signal. The LVEL14 is

functionally and pin compatible with the EL14 but is designed to operate

in ECL or PECL mode for a voltage supply range of –3.0V to –3.8V ( or

3.0V to 3.8V). If a single-ended input is to be used the V

output should

be connected to the CLK input and bypassed to ground via a 0.01µF

capacitor. The V output is designed to act as the switching reference

for the input of the LVEL14 under single-ended input conditions, as a

result this pin can only source/sink up to 0.5mA of current.

The LVEL14 features a multiplexed clock input to allow for the

distribution of a lower speed scan or test clock along with the high speed

system clock. When LOW (or left open and pulled LOW by the input

pulldown resistor) the SEL pin will select the differential clock input.

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D-04

The common enable (EN) is synchronous so that the outputs will only

be enabled/disabled when they are already in the LOW state. This avoids

any chance of generating a runt clock pulse when the device is

enabled/disabled as can happen with an asynchronous control. The

internal flip flop is clocked on the falling edge of the input clock, therefore

all associated specification limits are referenced to the negative edge of

the clock input.

• 50ps Output-to-Output Skew

• Synchronous Enable/Disable

• Multiplexed Clock Input

PIN DESCRIPTION

FUNCTION

• 75kΩ Internal Input Pulldown Resistors

• >2000V ESD Protection

CLK

SCLK

Diff Clock Inputs

Scan Clock Input

Sync Enable

• V

Range of –3.0V to –5.5V

SEL

Clock Select Input

Reference Output

Diff Clock Outputs

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

0–4

FUNCTION TABLE

NC SCLK CLK CLK

SEL

CLK

SCLK

SEL

* On next negative transition of

CLK or SCLK

7/95

REV 1

4–1

Motorola, Inc. 1996

12 3 4

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与MC100EL14相关器件

型号	品牌	获取价格	描述	数据表
MC100EL14_06	ONSEMI	获取价格	5V ECL 1:5 Clock Distribution Chip
MC100EL14DW	ONSEMI	获取价格	1:5 Clock Distribution Chip
MC100EL14DW	MOTOROLA	获取价格	1:5 Clock Distribution Chip
MC100EL14DWG	ONSEMI	获取价格	5V ECL 1:5 Clock Distribution Chip
MC100EL14DWR2	ONSEMI	获取价格	5V ECL 1:5 Clock Distribution Chip
MC100EL14DWR2G	ONSEMI	获取价格	5V ECL 1:5 Clock Distribution Chip
MC100EL15	ONSEMI	获取价格	1:4 Clock Distribution Chip
MC100EL15D	MOTOROLA	获取价格	1:4 Clock Distribution Chip
MC100EL15D	ONSEMI	获取价格	5V ECL 1:4 Clock Distribution Chip
MC100EL15DG	ONSEMI	获取价格	5V ECL 1:4 Clock Distribution Chip

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